DS1344E-18+ Maxim Integrated Products, DS1344E-18+ Datasheet - Page 16

• Manufacturer Part Number: DS1344E-18+
• Description: Real Time Clock SPI RTC 20P TSSOP 1.8V 12.5PF ALRM
• Manufacturer: Maxim Integrated Products

Figure 3. Serial Clock as a Function of Microcontroller Clock Polarity (CPOL)
Low-Current SPI/3-Wire RTCs
The serial peripheral interface (SPI) is a synchronous
bus for address and data transfer, and is used when
interfacing with the SPI bus on specific Motorola micro-
controllers, such as the 68HC05C4 and the 68HC11A8.
The SPI mode of serial communication is selected by
connecting SERMODE to V
SPI. The four pins are SDO (serial-data out), SDI (serial-
data in), CE (chip enable), and SCLK (serial clock). The
IC is the slave device in an SPI application, with the
microcontroller being the master.
SDI and SDO are the serial-data input and output pins,
respectively, for the device. The CE input is used to
initiate and terminate a data transfer. SCLK is used to
synchronize data movement between the master (micro-
controller) and the slave (IC) devices.
The input clock (SCLK), which is generated by the micro-
controller, is active only during address and data transfer
to any device on the SPI bus. The inactive clock polarity
is programmable in some microcontrollers. The device
determines the clock polarity by sampling SCLK when
CE becomes active. Therefore, either SCLK polarity can
be accommodated. Input data (SDI) is latched on the
internal strobe edge and output data (SDO) is shifted out
on the shift edge (Figure 3). There is one clock for each
bit transferred. Address and data bits are transferred in
groups of eight, MSB first.
16
Serial Peripheral Interface (SPI)
CPOL = 1
CPOL = 0
NOTE 1: CPHA BIT POLARITY (IF APPLICABLE) MAY NEED TO BE SET ACCORDINGLY.
NOTE 2: CPOL IS A BIT THAT IS SET IN THE MICROCONTROLLER’S CONTROL REGISTER.
NOTE 3: SDO REMAINS AT HIGH-Z UNTIL 8 BITS OF DATA ARE READY TO BE SHIFTED OUT DURING A READ.
CC
. Four pins are used for the
SCLK
SCLK
CE
SHIFT DATA OUT (READ)
SHIFT DATA OUT (READ)
Address and data bytes are shifted MSB first into the
serial-data input (SDI) and out of the serial-data output
(SDO). Any transfer requires the address of the byte to
specify a write or read to either a RTC or RAM location,
followed by one or more bytes of data. Data is trans-
ferred out of the SDO for a read operation and into the
SDI for a write operation (Figure 4 and Figure 5).
The address byte is always the first byte entered after CE
is driven high. The most significant bit (R/W) of this byte
determines if a read or write takes place. If R/W is 0, one
or more read cycles occur. If R/W is 1, one or more write
cycles occur.
Data transfers can occur 1 byte at a time or in multiple-
byte burst mode. After CE is driven high an address is
written to the device. After the address, one or more data
bytes can be written or read. For a single-byte transfer,
1 byte is read or written and then CE is driven low. For
a multiple-byte transfer, however, multiple bytes can
be read or written to the device after the address has
been written. Each read or write cycle causes the RTC
register or RAM address to automatically increment.
Incrementing continues until the device is disabled.
When the RTC address space is selected, the address
wraps to 00h after incrementing from 1Fh. When the
RAM address space is selected, the address wraps to
20h after incrementing from 7Fh.
DATA LATCH (WRITE)
DATA LATCH (WRITE)
Address and Data Bytes