CY28401OC Silicon Laboratories Inc, CY28401OC Datasheet - Page 8

no-image

CY28401OC

Manufacturer Part Number
CY28401OC
Description
Clock Buffer 100 MHz Diff Buffer PCIe & SATA 1in 4out
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of CY28401OC

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Rev 1.0, November 21, 2006
Output Enable Clarification
The OE function may be implemented in two ways, via writing
a ‘0’ to SMBus register bit corresponding to output of interest
or by asserting an OE input pin LOW. In both methods, if
SMBus registered bit has been written LOW or the OE pin is
LOW or both, the output of interest will be three-stated. (The
assertion and deassertion of this signal is absolutely
asynchronous.)
Table 6. OE Functionality
OE (Pin)#
DIFC(Free Running
DIFT(Free Running
DIFC(Free Running
DIFC(Free Running
DIFT(Free Running
DIFT(Free Running
DIFC (Stoppable)
DIFT (Stoppable)
DIFC (Stoppable)
DIFC (Stoppable)
DIFT (Stoppable)
DIFT (Stoppable)
SRC_STOP#
SRC_STOP#
SRC_STOP#
1
1
0
0
PWRDWN#
PWRDWN#
PWRDWN#
Figure 7. SRC_STOP# =Three-state, PWRDWN# = Three-state
Figure 5. SRC_STOP# =Driven, PWRDWN# = Three-state
Figure 6. SRC_STOP# =Three-state, PWRDWN# = Driven
OE (SMBus Bit)
1
0
1
0
Three-state
Three-state
Three-state
Normal
DIFT
1mS
1mS
1mS
Normal
DIFC
Low
Low
Low
CY28401
Page 8 of 13

Related parts for CY28401OC