CY28346ZXC-2 Silicon Laboratories Inc, CY28346ZXC-2 Datasheet - Page 17
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
CY28346ZXC-2
Manufacturer Part Number
CY28346ZXC-2
Description
Clock Synthesizer / Jitter Cleaner NB Clk Intel Brkdale 830M & 845 chipsets
Manufacturer
Silicon Laboratories Inc
Datasheet
1.CY28346ZXC-2.pdf
(19 pages)
Specifications of CY28346ZXC-2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY28346ZXC-2
Manufacturer:
CY
Quantity:
63
Part Number:
CY28346ZXC-2
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Rev 1.0, November 24, 2006
AC Parameters
Table 9. Maximum Lumped Capacitive Output Loads
T
T
T
T
T
T
Notes:
27. CPU_STP# and PCI _STP# set-up time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock’s rising edge
28. When crystal meets minimum 40Ω device series resistance specification.
29. Device is not affected, VTT_PWRGD# is ignored.
PZL
PZL
STABLE
SS
SH
SU
Parameter
VDD Clock Gen
/T
/T
VTT_PWRGD#
Clock Outputs
PZH
PZH
Clock State
Clock VCO
VID (0:3),
SEL (0,1)
PWRGD
Output Enable Delay
(All Outputs)
Output disable delay (all
outputs)
All Clock Stabilization
from Power-up
Stopclock Set-up Time
Stopclock Hold Time
Oscillator Start-up Time
(V
DD
Description
State 0
Off
Off
48MUSB Clock
= V
PCI Clocks
REF Clock
3V66 (0,1)
48MDOT
66B(0:2)
DDA
Clock
= 3.3V ±5%, T
0.2-0.3mS
Figure 16. VTT_PWRGD# Timing Diagram29
State 1
Delay
Min.
10.0
1.0
1.0
0
66 MHz
A
= 0°C to +70°C) (continued)
Max.
10.0
10.0
VTT_GD#
3
X
Wait for
On
Min.
10.0
1.0
1.0
0
100 MHz
Sample Sels
Max.
10.0
10.0
X
State 2
3
Max. Load
Min.
10.0
1.0
1.0
0
30
30
30
20
10
50
133 MHz
[29]
Max.
10.0
10.0
3
X
On
State 3
Min.
10.0
1.0
1.0
0
200 MHz
(Note A)
Max.
10.0
10.0
X
3
CY28346
Units
pF
pF
pF
pF
pF
pF
Page 17 of 19
Unit
ms
ms
ns
ns
ns
ns
Notes
10
10
10
27
27
28