MAX3872EGJ Maxim Integrated Products, MAX3872EGJ Datasheet - Page 11

• Manufacturer Part Number: MAX3872EGJ
• Description: Timers & Support Products Multirate Clock and Data Recovery with L
• Manufacturer: Maxim Integrated Products

Specifications of MAX3872EGJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The SDI± and SLBI± inputs of the MAX3872 are current-
mode logic (CML) compatible. The inputs all provide
internal 50Ω termination to reduce the required number
of external components. AC-coupling is recommended.
See Figure 8 for the input structure. For additional infor-
mation on logic interfacing, refer to Maxim Application
Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
The MAX3872 uses CML for its high-speed digital out-
puts (SDO± and SCLKO±). The configuration of the out-
put circuit includes internal 50Ω back terminations to
V
can be terminated by 50Ω to V
tial impedance. For additional information on logic inter-
facing, refer to Maxim Application Note HFAN 1.0:
Introduction to LVDS, PECL, and CML.
Figure 8. CML Input Model
SDI+
SDI-
CC
. See Figure 9 for the output structure. CML outputs
______________________________________________________________________________________
V
CC
MAX3872
50Ω
Output Terminations
50Ω
Input Terminations
Multirate Clock and Data Recovery
CC
, or by 100Ω differen-
Clock holdover is required in some applications in
which a valid clock must be provided to the upstream
device in the absence of data transitions. To provide
this function, an external reference clock signal must
be applied to the SLBI± inputs and the proper control
signals set (see the Modes of Operation section). To
enter holdover mode automatically when there are no
transitions applied to the SDI± inputs, LOL or the sys-
tem LOS can be directly connected to LREF.
The MAX3872 is designed to allow system loopback
testing. When the device is set for system loopback
mode, the serial output data of a transmitter may be
directly connected to the SLBI inputs to run system
diagnostics. See Table 1 for selecting system loopback
operation mode. While in system loopback mode, LREF
should not be connected to LOL.
with Limiting Amplifier
Figure 9. CML Output Model
MAX3872
50Ω
Applications Information
V
CC
Clock Holdover Capability
50Ω
System Loopback
SDO+
SDO-
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