Si5338K-A-GM Silicon Laboratories Inc, Si5338K-A-GM Datasheet - Page 12

• Manufacturer Part Number: Si5338K-A-GM
• Description: Clock Generators & Support Products I2C-PRGRMBL clock generatr 0.16-700MHz
• Manufacturer: Silicon Laboratories Inc

Specifications of Si5338K-A-GM

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5338
Table 12. Jitter Specifications
(V
12
Parameter
GbE Random Jitter
(12 kHz–20 MHz)
GbE Random Jitter
(1.875–20 MHz)
OC-12 Random Jitter
(12 kHz–5 MHz)
PCI Express 1.1 Common
Clocked
PCI Express 2.1 Common
Clocked
PCI Express 2.1 Data
Clocked
PCI Express 3.0 Common
Clocked
PCI Express 3.0 Data
Clocked
Period Jitter
Cycle-Cycle Jitter
Notes:
DD
1. All jitter measurements apply for LVDS/HCSL/LVPECL output format with a low noise differential input clock and are
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
3. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
4. D
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
7. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5 MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 2
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
differential clock input slew rates more than 0.3 V/ns.
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
See AN562 for details.
J
for PCI and GbE is < 5 ps pp
4
Symbol
R
J
1,2,3
J
J
J
OC12
JGbE
PER
GbE
CC
CLKIN = 25 MHz
All CLKn at 125 MHz
CLKIN = 25 MHz
All CLKn at 125 MHz
CLKIN = 19.44 MHz
All CLKn at
155.52 MHz
RMS Jitter
RMS Jitter
N = 10,000 cycles
N = 10,000 cycles
Output MultiSynth
operated in integer or
fractional mode
RMS Jitter
RMS Jitter
Test Condition
A
Rev. 1.0
RMS Jitter
RMS Jitter
Total Jitter
= –40 to 85 °C)
1.5 MHz
1.5 MHz
50 MHz
50 MHz
6
6
6
6
12
, 1.5 MHz to
, 1.5 MHz to
5
, 10 kHz to
, 10 kHz to
rising edges.
7
6
6
6
7
5
5
Min
—
—
—
—
—
—
—
—
—
—
—
—
0.38
0.49
0.25
0.65
0.79
0.15
0.17
11.2
Typ
0.7
0.7
10
9
Max
0.79
33.6
1.47
0.75
1.95
2.37
0.45
0.51
30
29
1
1
ps pk-pk
ps pk-pk
ps RMS
ps RMS
ps RMS
ps RMS
ps RMS
ps RMS
ps RMS
ps RMS
ps RMS
ps pk
Unit
8