CS4222-KS Cirrus Logic Inc, CS4222-KS Datasheet - Page 18

• Manufacturer Part Number: CS4222-KS
• Description: Audio CODECs IC 20-Bit Stereo Codec w/Vol Cntrl
• Manufacturer: Cirrus Logic Inc

Specifications of CS4222-KS

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 20 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC, 2 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS4222
4.3.2 Analog/Digital Volume Control (Control Port Mode only)
The DAC outputs are each routed through an attenuator which is adjustable in 0.5 dB steps. Output atten-
uation is available through the Output Attenuator Data Bytes (#3 & #4). Level changes are implemented with
an analog volume control until the residual output noise is equal to the noise floor in the mute state at which
point volume changes are performed digitally. This technique is superior to purely digital volume control
techniques as the noise is attenuated by the same amount as the signal, thus preserving dynamic range
(see Figure 8).
The CS4222 implements a "soft" volume control whereby level changes are achieved by ramping from the
current level to the new level in 0.5 dB steps. The default rate of volume change is 8 LRCK cycles for each
0.5 dB step (equivalent to 647 µs at Fs = 48 kHz). The rate of volume change is adjustable to 4, 16, or 32
LRCK cycles with the RMP1/0 bits in the DAC control byte (#2).
"Soft" volume control may be disabled through the SOFT bit in the DAC bit Control Byte (#2). When "soft"
volume control is defeated, level changes step from the current level to the new level in a single step. The
volume change takes effect on a zero crossing to minimize audible artifacts. If there is no zero crossing,
then the requested level change will occur after a time-out period between 512 and 1024 sample periods
(10.7 ms to 21.3 ms at 48 kHz sample rate). There is a separate zero crossing detector for each channel.
ACCR and ACCL bits in the Converter Status Report Byte (#6) give feedback when a volume control change
has taken effect for the right and left channel. This bit goes high when a new setting is loaded and returns
low when it has taken effect.
Analog Digital
0
Signal
Noise
0
-113.5
Attenuation (dB)
Figure 8. Hybrid Analog/Digital Attenuation
4.3.3 Soft Mute/Mute on Zero Input Data
Muting is achieved by hardware or software control. Soft mute can be achieved by lowering the SMUTE pin
at which point the output level will ramp down in 0.5 dB steps to a muted state. Upon returning the SMUTE
pin high, the output will ramp up to the volume control setting in the Output Attenuator Data Bytes (#3 & #4).
“Soft” mute may be disabled through the SOFT bit in the DAC Control Byte (#2). When “soft” mute is defeat-
ed, muting occurs on zero crossings or after a time-out period, similar to the volume control changes.
Under software control, each output can be independently muted via mute control bits, MUTR and MUTL,
in the DAC Control Byte (#2). Soft mute or zero crossing mute will be implemented depending on the state
of the SOFT bit in the DAC Control Byte (#2).
Muting on consecutive zero input data is also provided where all DAC outputs will mute if they receive be-
tween 512 and 1024 consecutive zeros (or -1 code). Detection and muting is done independently for left and
right channels. A single non-zero value will immediately unmute the DAC output. This feature is disabled on
power-up, and it may be enabled with the MUTC bit in the DAC Control Byte (#2).
18
DS236F1