CS5351-BZZR Cirrus Logic Inc, CS5351-BZZR Datasheet - Page 16

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CS5351-BZZR

Manufacturer Part Number
CS5351-BZZR
Description
Audio D/A Converter ICs IC 24Bit 108dB 192kHz Multi-Bit ADC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS5351-BZZR

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
16
4. APPLICATIONS
4.1
4.2
4.2.1
MCLK/LRCK Ratio
SCLK/LRCK Ratio
M1 (Pin 14)
Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2 kHz to 204 kHz. The CS5351 must be set to the proper
speed mode via the mode pins, M1 and M0. Refer to
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronous-
ly generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks.
The device also includes a master clock divider in Master Mode where the master clock will be internally
divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV
pin needs to be disabled, set to logic 0.
0
0
1
1
Slave Mode
LRCK and SCLK operate as inputs in Slave Mode. The left/right clock must be synchronously derived
from the master clock and be equal to Fs. It is also recommended that the serial clock be synchronously
derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to
for required clock ratios.
M0 (Pin 13)
0
1
0
1
Fs = 2 kHz to 51 kHz
Single-Speed Mode
Table 2. CS5351 Slave Mode Clock Ratios
32x, 64x, 128x
256x, 512x
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Reserved
Table 1. CS5351 Mode Control
MODE
Fs = 50 kHz to 102 kHz
Double-Speed Mode
Table
128x, 256x
32x, 64x
1.
2 kHz - 51 kHz
50 kHz - 102 kHz
100 kHz - 204 kHz
Output Sample Rate (Fs)
Fs = 100 kHz to 204 kHz
Quad-Speed Mode
32x, 64x
128x
CS5351
DS565F2
Table 2

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