CS4224-KSZR Cirrus Logic Inc, CS4224-KSZR Datasheet - Page 16
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CS4224-KSZR
Manufacturer Part Number
CS4224-KSZR
Description
Audio CODECs IC 24-Bit 105dB Ster Cod w/o Vol Con
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS4224-KSZR.pdf
(34 pages)
Specifications of CS4224-KSZR
Number Of Adc Inputs
2
Number Of Dac Outputs
2
Conversion Rate
48 KSPs
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC, 2 DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
5.1.6
5.2
5.2.1
5.2.2
5.2.3
16
Reserved
7
0
CLOCKING ERROR (CLKE) (READ ONLY)
DAC Control (address 02h)
MUTE ON CONSECUTIVE ZEROS (MUTC)
MUTE CONTROL (MUTR-MUTL)
SOFT RAMP CONTROL (SOFT)
Function:
Function:
Function:
Default = 0
0 - No error
1 - Error
Default = 0
0 - Disabled
1 - Enabled
The DAC output will mute following the reception of 512 consecutive audio samples of static 0 or -1
when this function is enabled. A single sample of non-static data will release the mute. Detection and
muting is done independently for each channel. The muting function is affected, similar to volume
control changes, by the SOFT bit in the DAC Control register.
Default = 0
0 - Disabled
1 - Enabled
The output for the selected DAC channel will be muted when this function is enabled. The muting
function is affected, similar to volume control changes, by the SOFT bit in the DAC Control register.
Default = 0
0 - Soft Ramp level changes
1 - Zero Cross level changes
Soft Ramp level changes will be implemented by incrementally ramping, in 0.5 dB steps, from the cur-
rent level to the new level. The rate of change defaults to 0.5 dB per 8 left/right clock periods and is
adjustable through the RMP bits in the DAC Control register.
Zero Cross level changes will be implemented in a single step from the current level to the new level.
The level change takes effect on a zero crossing to minimize audible artifacts. If the signal does not
encounter a zero crossing, the level change will occur after a timeout period of 512 sample periods
(10.7 ms at 48 kHz sample rate). Zero crossing is independently monitored and implemented for each
channel. The ACCR and ACCL bits in the Converter Status Report register indicate when a level
change has occurred for the right and left channel.
MUTC
6
0
MUTR
5
0
MUTL
4
0
SOFT
3
0
Reserved
2
0
RMP1
CS4223 CS4224
1
0
RMP0
DS290F1
0
0