CS8420-DSR Cirrus Logic Inc, CS8420-DSR Datasheet - Page 85
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CS8420-DSR
Manufacturer Part Number
CS8420-DSR
Description
Audio DSPs IC Digital Audio Sample Rate Convertr
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS8420-CSZ.pdf
(94 pages)
Specifications of CS8420-DSR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
DS245F4
15.2.3 IEC60958 Recommended U Data Format for Consumer Applications
15.2.4 Mode (3): Reserved
15.2.5 Mode (4): IEC Consumer B
transmitted bit. The first byte read is the first byte received, and the first byte sent is the first byte trans-
mitted.
Modes (3) and (4) are intended for use in AES3 in, AES3 out situations, in which the input U data is for-
matted as recommended in the “IEC60958 Digital Audio Interface, part 3: Consumer applications” docu-
ment.
In this format, “messages” are formed in the U data from Information Units or IUs. An IU is 8 bits long, and
the MSB is always 1, and is called the start bit, or 'P' bit. The remaining 7-bits are called Q, R, S, T, U, V,
& W, and carry the desired data.
A “message” consists of 3 to 129 IUs. Multiple IUs are considered to be in the same message if they are
separated by 0 to 8 zeros, denoted here as filler. A filler sequence of nine or more zeros indicates an inter-
message gap. The desired information is normally carried in the sequence of corresponding bits in the
IUs. For example, the sequential Q bits from each IU make up the Q sub-code data that is used to indicate
Compact Disk track information. This data is automatically extracted from the received IEC60958 stream,
and is presented in the control port register map space.
Where incoming U data is coded in the above format, and needs to be re-transmitted, the data transfer
cannot be done using shift registers, because of the different Fsi and Fso sampling clocks. Instead, input
data must be buffered in a FIFO structure, and then read out by the AES3 transmitter at appropriate times.
Each bit of each IU must be transceived; unlike the audio samples, there can be no sample rate conver-
sion of the U data. Therefore, there are two potential problems:
(1) Message Partitioning
When Fso > Fsi, more data is transmitted than received per unit time. The FIFO will frequently be com-
pletely emptied. Sensible behavior must occur when the FIFO is empty, otherwise, a single incoming mes-
sage may be erroneously partitioned into multiple, smaller, messages.
(2) Overwriting
When Fso < Fsi, more data is received than transmitted per unit time. There is a danger of the FIFO be-
coming completely full, allowing incoming data to overwrite data that has not yet been output through the
AES3 transmitter.
This mode has been removed. Use IEC Consumer mode B.
In this mode, the partitioning problem is solved by buffering an entire message before starting to transmit
it. In this scheme, zero-segments between messages will be expanded when Fso > Fsi, but the integrity
of individual messages is preserved.
The overwriting problem (when Fso < Fsi) is solved by only storing a portion of the input U data in the
FIFO. Specifically, only the IUs themselves are stored (and not the zeros that provide inter-IU and inter-
message “filler”). An inter-IU filler segment of fixed length (OF) will be added back to the messages at the
FIFO output, where the length of OF is equal to the shortest observed input filler segment (IF).
Storing only IUs (and not filler) within the FIFO makes it possible for the slower AES3 transmitter to “catch
up” to the faster AES3 receiver as data is read out of the FIFO. This is because nothing is written into the
FIFO when long strings of zeros are input to the AES-EBU receiver. During this time of no writing, the
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