CS42526-CQZR Cirrus Logic Inc, CS42526-CQZR Datasheet - Page 6

• Manufacturer Part Number: CS42526-CQZR
• Description: Audio CODECs IC 114dB 192kHz 6Ch Mlt-Ch CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CS42526-CQZR

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 6
• Conversion Rate: 192 KSPs
• Interface Type: Serial (SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC, 6 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CS42526
LIST OF TABLES
Table 1. Common OMCK Clock Frequencies ............................................................................................ 26
Table 2. Common PLL Output Clock Frequencies..................................................................................... 26
Table 3. Slave Mode Clock Ratios ............................................................................................................. 27
Table 4. Serial Audio Port Channel Allocations ......................................................................................... 28
Table 5. DAC De-Emphasis ....................................................................................................................... 49
Table 6. Receiver De-Emphasis ................................................................................................................ 49
Table 7. Digital Interface Formats .............................................................................................................. 50
Table 8. ADC One-Line Mode.................................................................................................................... 50
Table 9. DAC One-Line Mode.................................................................................................................... 50
Table 10. RMCK Divider Settings .............................................................................................................. 53
Table 11. OMCK Frequency Settings ........................................................................................................ 53
Table 12. Master Clock Source Select....................................................................................................... 54
Table 13. AES Format Detection ............................................................................................................... 55
Table 14. Receiver Clock Frequency Detection......................................................................................... 56
Table 15. Example Digital Volume Settings ............................................................................................... 59
Table 16. ATAPI Decode ........................................................................................................................... 61
Table 17. Example ADC Input Gain Settings ............................................................................................. 62
Table 18. TXP Output Selection................................................................................................................. 64
Table 19. Receiver Input Selection ............................................................................................................ 64
Table 20. Auxiliary Data Width Selection ................................................................................................... 67
Table 21. External PLL Component Values & Locking Modes .................................................................. 78
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