WM8350GEB/RV Wolfson Microelectronics, WM8350GEB/RV Datasheet - Page 97

• Manufacturer Part Number: WM8350GEB/RV
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8350GEB/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
13.11 COMPANDING
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The WM8350 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC)
sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate
value to the DAC_COMP or ADC_COMP register bits respectively.
Table 49 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out
by ITU-T G.711 standard) for data compression:
μ-law (where μ=255 for the U.S. and Japan):
F(x) = ln( 1 + μ|x|) / ln( 1 + μ)
law (where A=87.6 for Europe):
F(x) = A|x| / ( 1 + lnA)
F(x) = ( 1 + lnA|x|) / (1 + lnA)
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for μ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs
of data.
Companding converts 13 bits (μ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This
provides greater precision for low amplitude signals than for high amplitude signals, resulting in a
greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word
comprising sign (1 bit), exponent (3 bits) and mantissa (4-bits).
8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows
samples to be passed using as few as 8 BCLK cycles per LRCLK frame. When using DSP mode B,
8-bit data words may be transferred consecutively every 8 BCLK cycles.
8-bit mode (without Companding) may be enabled by setting DAC_COMPMODE=1 or
ADC_COMPMODE=1 when DAC_COMP=0 and ADC_COMP=0.
Table 50 8-bit Companded Word Composition
R113 (71h)
Companding
Control
REGISTER
ADDRESS
BIT7
SIG
N
BIT
4
5
6
7
EXPONENT
BIT[6:4]
ADC_COMPM
ODE
ADC_COMP
DAC_COMPM
ODE
DAC_COMP
LABEL
-1 ≤ x ≤ 1
} for x ≤ 1/A
} for 1/A ≤ x ≤ 1
DEFAULT
0
0
0
0
ADC Companding mode select:
0 = μ-law
1 = A-law
(Note: Setting ADC_COMPMODE=1
selects 8-bit mode when DAC_COMP=0
and ADC_COMP=0)
ADC Companding enable
0 = disabled
1 = enabled
DAC Companding mode select:
0 = μ-law
1 = A-law
(Note: Setting DAC_COMPMODE=1
selects 8-bit mode when DAC_COMP=0
and ADC_COMP=0)
DAC Companding enable
0 = disabled
1 = enabled
BIT[3:0]
MANTISSA
DESCRIPTION
PD, February 2011, Rev 4.4
WM8350
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