WM9705SEFT/RV Wolfson Microelectronics, WM9705SEFT/RV Datasheet - Page 29

• Manufacturer Part Number: WM9705SEFT/RV
• Description: Audio CODECs Stereo AC'97 Codec T/P Interface
• Manufacturer: Wolfson Microelectronics

Specifications of WM9705SEFT/RV

• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Conversion Rate: 48 KSPs
• Interface Type: AC97
• Resolution: 12 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC, 2 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM9705
AC-LINK LOW POWER MODE
WAKING UP THE AC-LINK
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SLOTS 7 AND 8:
These data slots may be utilised by the WM9705 to output audio data under control of the
mapping bits ASS [1:0] in register 5Ch, allowing implementation of multi-channel systems. These
slots may also be used to output Pen ADC data.
SLOTS 10 AND 11:
These data slots may be utilised by the WM9705 to output audio data under control of the
mapping bits ASS[1:0] in register 5Ch, allowing implementation of multi-channel systems. These
slots may also be used to output Pen ADC data.
SLOT 12:
Pen digitiser data may be mapped onto this slot as MSB justified words, under control of register
76h. Alternatively pen input data can also be read from register 7Ah.
The AC-link signals can be placed in a low power mode. When the WM9705’s Powerdown
Register 26h, is programmed to the appropriate value, both BITCLK and SDATAIN will be brought
to, and held at a logic low voltage level.
BITCLK and SDATAIN are transitioned low immediately following the decode of the write to the
Powerdown Register (26h) with PR4. When the AC’97 controller driver is at the point where it is
ready to program the AC-link into its low power mode, slots 1 and 2 are assumed to be the only
valid stream in the audio output frame. At this point in time it is assumed that all sources of audio
input have also been neutralised.
The AC’97 controller should also drive SYNC and SDATAOUT low after programming the
WM9705 to this low power, halted mode.
Once the WM9705 has been instructed to halt BITCLK, a special wake up protocol must be used
to bring the AC-link to the active mode since normal audio output and input frames can not be
communicated in the absence of BITCLK.
In addition to the standard AC’97 wake-up protocol, the WM9705 also supports a wake-up after a
pen-down status has been determined.
There are 3 methods for bringing the AC-link out of a low power, halted mode.
AC-link protocol provides for a Cold WM9705 Reset, a Warm WM9705 Reset and a Pen Down
Detect Warm Reset.
The current Powerdown state would ultimately dictate which form of WM9705 reset is appropriate.
Unless a cold or register reset (a write to the Reset Register 00h) is performed, wherein the
WM9705 registers are initialised to their default values, registers are required to keep state during
all Powerdown modes.
Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not
occur for a minimum of 4 audio frame times following the frame in which the Powerdown was
triggered. When AC-link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit
15).
COLD WM9705 RESET
A cold reset is achieved by asserting RESETB for the minimum specified time. By driving
RESETB low, BITCLK, and SDATAOUT will be activated, or re-activated as the case may be, and
all the WM9705 control registers will be initialised to their default power on reset values.
RESETB is an asynchronous WM9705 input.
WARM WM9705 RESET
A warm WM9705 reset will re-activate the AC-link without altering the current WM9705 register
values. A warm reset is signaled by driving SYNC high for a minimum of 1 µ s in the absence of
BITCLK.
PD Rev 4.5 July 2008
Production Data
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