WM8973LGEFL/V Wolfson Microelectronics, WM8973LGEFL/V Datasheet - Page 52

• Manufacturer Part Number: WM8973LGEFL/V
• Description: Audio CODECs Stereo Codec with H/P Spkr
• Manufacturer: Wolfson Microelectronics

Specifications of WM8973LGEFL/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8973L
w
REGISTER
R10 (0Ah)
R11 (0Bh)
R12 (0Ch)
R13 (0Dh)
R26 (1Ah)
R27 (1Bh)
R42 (2Ah)
R15 (0Fh)
R16 (10h)
R17 (11h)
R18 (12h)
R19 (13h)
R20 (14h)
R21 (15h)
R22 (16h)
R23 (17h)
R24 (18h)
R25 (19h)
R31 (1Fh)
R32 (20h)
R33 (21h)
R34 (22h)
R35 (23h)
R36 (24h)
R37 (25h)
R38 (26h)
R39 (27h)
R40 (28h)
R41 (29h)
R0 (00h)
R1 (01h)
R2 (02h)
R3 (03h)
R4 (04h)
R5 (05h)
R6 (06h)
R7 (07h)
R8 (08h)
R9 (09h)
REGISTER MAP
(Bit 15 – 9)
ADDRESS
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
Additional Control (3)
ADC & DAC Control ADCDIV2 DACDIV2
Additional control(1)
Additional control(2)
MONOOUT volume
Right Input volume
Right DAC volume
Right ADC volume
ADCR signal path
ADCL signal path
Left Input volume
Left DAC volume
Left ADC volume
Mono out Mix (1)
Mono out Mix (2)
ADC input mode
Right out Mix (1)
Right out Mix (2)
ROUT1 volume
Left out Mix (1)
ROUT2 volume
LOUT1 volume
Audio Interface
Left out Mix (2)
LOUT2 volume
Treble control
Pwr Mgmt (1)
Pwr Mgmt (2)
Sample rate
Bass control
Noise Gate
3D control
Reserved
Reserved
Reserved
remarks
Reset
ALC1
ALC2
ALC3
RD2RO
RD2MO
RO1VU
TSDEN
RD2LO
LD2RO
LD2MO
RO2VU
LO1VU
LD2LO
LO2VU
RDVU
RAVU
LDVU
LAVU
DACL
Bit[8]
RIVU
LIVU
OUT3SW[1:0]
VMIDSEL[1:0]
ADCLRM[1:0]
DS
ALCSEL[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
BCM[1:0]
RINMUTE
LINMUTE
BCLKINV
MODE3D
RO1ZC
RO2ZC
LO1ZC
ALCZC
LO2ZC
RI2RO
LI2MO
RI2MO
DACR
RI2LO
LI2RO
MOZC
LI2LO
Bit[7]
MONOMIX[1:0]
BB
RINSEL[1:0]
LINSEL[1:0]
0
0
0
0
VSEL[1:0]
writing to this register resets all registers to their default state
HPSWEN HPSWPOL ROUT2INV
CLKDIV2
LOUT1
3DUC
Bit[6]
VREF
VROI
LIZC
RIZC
MS
ADCPOL[1:0]
BC
TC
0
0
0
0
DCY[3:0]
RI2MOVOL[2:0]
RI2ROVOL[2:0]
LI2MOVOL[2:0]
RI2LOVOL[2:0]
LI2ROVOL[2:0]
MAXGAIN[2:0]
LI2LOVOL[2:0]
NGTH[4:0]
LRSWAP
HPFLREN
ROUT1
LMICBOOST[1:0]
RMICBOOST[1:0]
RDCM
DMONOMIX[1:0]
Bit[5]
3DLC
AINL
0
0
0
0
0
0
LOUT2
HPOR
LDCM
Bit[4]
AINR
LRP
RDACVOL[7:0]
RADCVOL[7:0]
LDACVOL[7:0]
LADCVOL[7:0]
0
0
0
0
0
0
0
ROUT1VOL[6:0]
ROUT2VOL[6:0]
LOUT1VOL[6:0]
LOUT2VOL[6:0]
MOUTVOL[6:0]
DACMU
SR[4:0]
ROUT2
ADCL
Bit[3]
3DDEPTH[3:0]
TRI
DATSEL[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
WL[1:0]
RINVOL
LINVOL
MONO
LRCM
ADCR
Bit[2]
DEEMPH[1:0]
NGG[1:0]
0
0
0
0
0
0
0
0
0
0
0
BASS[3:0]
TRBL[3:0]
ALCL[3:0]
HLD[3:0]
ATK[3:0]
RMIXSEL[2:0]
LMIXSEL[2:0]
ADCOSR DACOSR
DACINV
Bit[1]
OUT3
MICB
0
0
0
0
0
0
0
FORMAT[1:0]
0
0
0
0
ADCHPD
DIGENB
PD, Rev 4.5, December 2011
NGAT
Bit[0]
3DEN
TOEN
USB
0
0
0
0
0
0
0
0
0
0
0
0
001111001
010010111
010010111
001111001
001111001
000000000
000001000
000000000
000001010
000000000
000000000
011111111
011111111
000001111
000001111
000000000
001111011
000000000
000110010
000000000
011000011
011000011
011000000
000000000
000000000
000000000
000000000
000000000
000000000
000000000
001010000
001010000
001010000
001010000
001010000
001010000
001111001
001111001
not reset
default
Production Data
36, 38,Error!
not defined.
21,22,32,39
Bookmark
page ref
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