UPA505T-T1-A Renesas Electronics America, UPA505T-T1-A Datasheet - Page 3

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UPA505T-T1-A

Manufacturer Part Number
UPA505T-T1-A
Description
MOSFET N/P-CH 50V 8-SOIC
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPA505T-T1-A

Fet Type
N and P-Channel
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
25 Ohm @ 10mA, 10V
Drain To Source Voltage (vdss)
50V
Current - Continuous Drain (id) @ 25° C
100mA
Vgs(th) (max) @ Id
1.8V @ 1µA
Input Capacitance (ciss) @ Vds
16pF @ 5V
Power - Max
300mW
Mounting Type
Surface Mount
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Gate Charge (qg) @ Vgs
-
Document No. G11241EJ1V0DS00 (1st edition)
Date Published June 1996 P
Printed in Japan
MOS FET circuits. It achieves high-density mounting and
saves mounting costs.
FEATURES
• Two source common MOS FET circuits in package the
• Complementary MOS FETs are provided in one package.
• Automatic mounting supported
ABSOLUTE MAXIMUM RATINGS (T
Drain to Source Voltage
Gate to Source Voltage
Drain Current (DC)
Drain Current (pulse)
Total Power Dissipation
Channel Temperature
Storage Temperature
The PA505T is a mini-mold device provided with two
same size as SC-59
* PW
Note The left and right values in the ratings column are correspond to N-ch and P-ch FETs, respectively.
10 ms, Duty Cycle
PARAMETER
N-CHANNEL/P-CHANNEL MOS FET (5-PIN 2 CIRCUITS)
50 %
SYMBOL
V
V
I
I
P
T
T
D(DC)
D(pulse)
ch
stg
DSS
GSS
T
DATA SHEET
A
*
= 25 ˚C)
MOS FIELD EFFECT TRANSISTOR
300 (TOTAL)
–55 to +150
RATINGS
100/+ – 100
200/+ – 200
50/–50
20/+ – 16
150
PACKAGE DIMENSIONS (in millimeters)
0.32
+0.1
–0.05
PIN CONNECTION (Top View)
0.95
2.9 ±0.2
1.9
UNIT
mW
mA
mA
˚C
˚C
V
V
0.95
PA505T
Marking: FA
1.1 to 1.4
0.8
0.16
0 to 0.1
+0.1
–0.06
1996

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