LTC4259ACGW-1#TR Linear Technology, LTC4259ACGW-1#TR Datasheet - Page 26

• Manufacturer Part Number: LTC4259ACGW-1#TR
• Description: IC,Power Control/Management,CMOS,SOP,36PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4259ACGW-1#TR

• Linear Misc Type: Negative Voltage
• Family Name: LTC4259A
• Package Type: SSOP
• Operating Supply Voltage (min): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC4259A-1
direction. A STOP condition is not used to set up a
REPEATED START condition, for this would clear any data
already latched in. When the master has finished commu-
nicating with the slave, it issues a STOP condition. A STOP
condition is generated by transitioning SDA from low to
high while SCL is high. The bus is then free for communi-
cation with another SMBus or I
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The corresponding SCL
clock pulse is always generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave must pull down the SDA line during
the Acknowledge clock pulse so that it remains a stable
LOW during the HIGH period of this clock pulse. When the
master is reading from a slave device, it is the master’s
responsibility to acknowledge receipt of the data byte in
the bit that follows unless the transaction is complete. In
that case the master will decline to acknowledge and issue
the STOP condition to terminate the communication.
Write Byte Protocol
The master initiates communication to the LTC4259A-1
with a START condition and a 7-bit bus address followed
by the Write Bit (Wr) = 0. If the LTC4259A-1 recognizes its
own address, it acknowledges and the master delivers the
command byte, signifying to which internal LTC4259A-1
register the master wishes to write. The LTC4259A-1 ac-
knowledges and latches the lower five bits of the com-
mand byte into its Register Address register. Only the lower
five bits of the command byte are checked by the LTC4259A-
1; the upper three bits are ignored. The master then deliv-
ers the data byte. The LTC4259A-1 acknowledges once
more and latches the data into the appropriate control
register. Finally, the master terminates the communica-
tion with a STOP condition. Upon reception of the STOP
condition, the Register Address register is cleared (see
Figure 7).
26
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U
2
C device.
W
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Read Byte Protocol
The master initiates communication from the LTC4259A-
1 with a START condition and the same 7-bit bus address
followed by the Write Bit (Wr) = 0. If the LTC4259A-1
recognizes its own address, it acknowledges and the
master delivers the command byte, signifying which
internal LTC4259A-1 register it wishes to read from. The
LTC4259A-1 acknowledges and latches the lower five bits
of the command byte into its Register Address register. At
this time the master sends a REPEATED START condition
and the same 7-bit bus address followed by the Read Bit
(Rd) = 1. The LTC4259A-1 acknowledges and sends the
contents of the requested register. Finally, the master
declines to acknowledge and terminates communication
with a STOP condition. Upon reception of the STOP
condition, the Register Address register is cleared (see
Figure 8).
Receive Byte Protocol
Since the LTC4259A-1 clears the Register Address regis-
ter on each STOP condition, the interrupt register (register
0) may be read with the Receive Byte Protocol as well as
with the Read Byte Protocol. In this protocol, the master
initiates communication with the LTC4259A-1 with a
START condition and a 7-bit bus address followed by the
Read Bit (Rd) = 1. The LTC4259A-1 acknowledges and
sends the contents of the interrupt register. The master
then declines to acknowledge and terminates communi-
cation with a STOP condition (see Figure 9).
Alert Response Address and the INT Pin
In a system where several LTC4259A-1s share a common
INT line, the master can use the Alert Response Address
(ARA) to determine which LTC4259A-1 initiated the
interrupt.
The master initiates the ARA procedure with a START
condition and the 7-bit ARA bus address (0001100)b
followed by the Read Bit (Rd) = 1. If an LTC4259A-1 is
asserting the INT pin, it acknowledges and sends its 7-bit
bus address (010A
While it is sending its address, it monitors the SDAIN pin
to see if another device is sending an address at the same
3
A
2
A
1
A
0
)b and a 1 (see Figure 10).
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