LTC3703IGN-5 Linear Technology, LTC3703IGN-5 Datasheet - Page 25

• Manufacturer Part Number: LTC3703IGN-5
• Description: IC,SMPS CONTROLLER,VOLTAGE-MODE,CMOS,SSOP,16PIN,PLASTIC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
oscillator can synchronize to frequencies between 100kHz
and 600kHz, independent of the frequency programmed
by the R
R
grammed by the R
frequency of the external clock. In this way, the best
converter operation (ripple, component stress, etc) is
achieved if the external clock signal is lost.
Fault Conditions: Output Overvoltage Protection
(Crowbar)
The output overvoltage crowbar is designed to blow a
system fuse in the input lead when the output of the
regulator rises much higher than nominal levels. This
condition causes huge currents to flow, much greater than
in normal operation. This feature is designed to protect
against a shorted top MOSFET; it does not protect against
a failure of the controller itself.
The comparator (MAX in the Functional Diagram) detects
overvoltage faults greater than 5% above the nominal
output voltage. When this condition is sensed the top
MOSFET is turned off and the bottom MOSFET is forced
on. The bottom MOSFET remains on continuously for as
long as the 0V condition persists; if V
level, normal operation automatically resumes.
Minimum On-Time Considerations (Buck Mode)
Minimum on-time t
that the LTC3703 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required to turn on the top
MOSFET. Low duty cycle applications may approach this
minimum on-time limit and care should be taken to ensure
that:
where t
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3703 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency opera-
tion is acceptable, the on-time can be increased above
t
ON(MIN)
SET
t
ON
resistor be chosen such that the frequency pro-
=
ON(MIN)
SET
for the same step-down ratio.
V
V
IN
OUT
resistor. However, it is recommended that an
•
f
is typically 200ns.
>
t
ON MIN
ON(MIN)
SET
U
(
resistor is close to the expected
)
U
is the smallest amount of time
W
OUT
returns to a safe
U
Pin Clearance/Creepage Considerations
The LTC3703 is available in two packages (GN16 and G28)
both with identical functionality. The GN16 package gives
the smallest size solution, however the 0.013” (minimum)
space between pins may not provide sufficient PC board
trace clearance between high and low voltage pins in
higher voltage applications. Where clearance is an issue,
the G28 package should be used. The G28 package has 4
unconnected pins between the all adjacent high voltage
and low voltage pins, providing 5(0.0106”) = 0.053”
clearance which will be sufficient for most applications up
to 100V. For more information, refer to the printed circuit
board design standards described in IPC-2221
(www.ipc.org).
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power (x100%). Per-
cent efficiency can be expressed as:
where L1, L2, etc. are the individual losses as a percentage
of input power. It is often useful to analyze the individual
losses to determine what is limiting the efficiency and
what change would produce the most improvement. Al-
though all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3703 circuits: 1) LTC3703 V
MOSFET gate current, 3) I
transition losses.
1. V
current given in the Electrical Characteristics table which
powers the internal control circuitry of the LTC3703. Total
supply current is typically about 2.5mA and usually results
in a small (<1%) loss which is proportional to V
2. DRV
results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched on and
then off, a packet of gate charge Q
ground. The resulting dQ/dt is a current out of the DRV
supply. In continuous mode, I
where Q
and bottom MOSFETs.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
CC
Supply current. The V
CC
G(TOP)
current is MOSFET driver current. This current
and Q
G(BOT)
2
are the gate charges of the top
R losses, 4) Topside MOSFET
DRVCC
CC
current is the DC supply
G
moves from DRV
= f(Q
LTC3703
G(TOP)
CC
current, 2)
+ Q
CC
G(BOT)
25
.
CC
3703fa
CC
to
),