LTC2632CTS8-HZ12#TRMPBF Linear Technology, LTC2632CTS8-HZ12#TRMPBF Datasheet - Page 18

• Manufacturer Part Number: LTC2632CTS8-HZ12#TRMPBF
• Description: MS-DAC/Industrial, 12-Bit SPI Dual DAC ( 2.5LSB Max INL, 4.096V Ref, Reset To Z
• Manufacturer: Linear Technology

Specifications of LTC2632CTS8-HZ12#TRMPBF

• Input Channel Type: Serial
• Data Interface: 3-Wire, Serial
• Supply Voltage Range - Analog: 4.5V To 5.5V
• Supply Current: 500µA
• Digital Ic Case Style: TSOT-23
• No. Of Pins: 8
• Rohs Compliant: Yes
• Resolution (bits): 12bit

LTC2632
OPERATION
Serial Interface
The CS/LD input is level triggered. When this input is
taken low, it acts as a chip-select signal, enabling the SDI
and SCK buffers and the input shift register. Data (SDI
input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first; then the 4-bit
DAC address, A3-A0; and finally the 16-bit data word.
The data word comprises the 12-, 10- or 8-bit input code,
ordered MSB-to-LSB, followed by 4, 6 or 8 don’t-care bits
(LTC2632-12, LTC2632-10 and LTC2632-8 respectively;
see Figure 2). Data can only be transferred to the device
when the CS/LD signal is low, beginning on the first rising
edge of SCK. SCK may be high or low at the falling edge
of CS/LD. The rising edge of CS/LD ends the data transfer
and causes the device to execute the command specified
in the 24-bit input sequence. The complete sequence is
shown in Figure 3a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Tables 1 and 2. The first four commands in
Table 1 consist of write and update operation. A Write
18
INPUT WORD (LTC2632-12)
INPUT WORD (LTC2632-10)
INPUT WORD (LTC2632-8)
C3
C3
C3
COMMAND
COMMAND
COMMAND
C2
C2
C2
C1
C1
C1
C0
C0
C0
A3
A3
A3
ADDRESS
ADDRESS
ADDRESS
A2
A2
A2
A1
A1
A1
A0
A0
A0
Figure 2. Command and Data Input Format
MSB
MSB
MSB
D11
D9
D7
D10
D8
D6
D9
D7
D5
D8
D6
D4
D7
D5
D3
operation loads a 16-bit data word from the 24-bit shift
register into the input register of the selected DAC, n. An
Update operation copies the data word from the input
register to the DAC register. Once copied into the DAC
register, the data word becomes the active 12-, 10-, or
8-bit input code, and is converted to an analog voltage at
the DAC output. Write to and Update combines the first
two commands. The Update operation also powers up the
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
While the minimum input sequence is 24 bits, it may
optionally be extended to 32 bits to accommodate micro-
processors that have a minimum word width of 16 bits (2
bytes). To use the 32-bit width, 8 don’t-care bits are trans-
ferred to the device first, followed by the 24-bit sequence
described. Figure 3b shows the 32-bit sequence.
The 16-bit data word is ignored for all commands that do
not include a Write operation.
DATA (12 BITS + 4 DON’T-CARE BITS)
DATA (10 BITS + 6 DON’T-CARE BITS)
DATA (8 BITS + 8 DON’T-CARE BITS)
D6
D4
D2
D5
D3
D1
D4
D2
D0
LSB
D3
D1
X
D2
D0
LSB
X
D1
X
X
D0
X
X
LSB
X
X
X
X
X
X
X
X
X
2632 F02
X
X
X
2632fa