LTC2442IG Linear Technology, LTC2442IG Datasheet - Page 20

• Manufacturer Part Number: LTC2442IG
• Description: IC,A/D CONVERTER,SINGLE,24-BIT,CMOS,SSOP,36PIN
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins
on this fi rst rising edge of SCK and concludes after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the fi rst rising edge of SCK and the last bit of
the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
LTC2442
20
BUSY
SDO
SCK
SDI
CS
DON'T CARE
U
CONVERSION
U
BIT 31
EOC
1
1
Figure 8. Internal Serial Clock, Reduced Data Output Length
EOCtest
SLEEP
BIT 30
W
“0”
2
0
0.1V TO V
REFERENCE
ANALOG
BIT 29
INPUTS
VOLTAGE
SIG
EN
0.1µF
0.1µF
, the fi rst rising
3
1µF
4.5V TO 5.5V
CC
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
MSB
SGL
4
U
29
30
31
28
12
13
11
17
18
10
6
7
8
9
ODD
V
REF
REF
CH0
CH1
CH2
CH3
COM
OUTA
–INA
ADCINA
OUTB
–INB
ADCINB
CC
5
+
–
LTC2442
MUXOUTA
MUXOUTB
0
6
BUSY
+INA
+INB
SDO
GND
SCK
EXT
SDI
CS
V
F
V
7
0
O
+
–
DATA OUTPUT
CS HIGH anytime between the fi rst and 32nd rising edge
of SCK, see Figure 8. On the rising edge of CS, the device
aborts the data output state and immediately initiates a new
conversion. This is useful for systems not requiring all 32
bits of output data, aborting an invalid conversion cycle,
or synchronizing the start of a conversion. Thirteen serial
input data bits are required in order to properly program
the speed/resolution and input channel. If the data output
sequence is aborted prior to the 13th rising edge of SCK,
the new input data is ignored, and the previously selected
speed/resolution and channel are used for the next con-
version cycle. If a new channel is being programmed, the
rising edge of CS must come after the 14th falling edge of
SCK in order to store the data input sequence.
V
21
27
25
26
19
24
4, 5, 32
CC
33
36
35
34
3
1
2
TO 15V
A0
8
–15V TO GND
1µF
V
CC
OSR3
4-WIRE
SPI INTERFACE
9
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
OSR2
10
OSR1
11
BIT 20 BIT 19
OSR0 TWOX
12
13
14
BIT 0
DON'T CARE
15
32
2442 F08
CONVERSION
2442f