CYIL2SM1300AA-GZDC Cypress Semiconductor Corp, CYIL2SM1300AA-GZDC Datasheet - Page 12

• Manufacturer Part Number: CYIL2SM1300AA-GZDC
• Description: IMAGE SENSOR CMOS LUPA-1300-3
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYIL2SM1300AA-GZDC

• Package / Case: 168-PGA
• Pixel Size: 14µm x 14µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 500
• Voltage - Supply: 2.5V, 3.3V
• Operating Supply Voltage: 2.5 V
• Maximum Power Dissipation: 1350 mW
• Maximum Operating Temperature: + 70 C
• Supply Current: 80 mA
• Minimum Operating Temperature: 0 C
• Package: 168CuPGA
• Image Size: 1280x1024 Pixels
• Color Sensing: Monochrome
• Operating Temperature: 0 to 70 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 9. Internal Registers (continued)
Document Number: 001-24599 Rev. *F
Bias block
Image Core
Data Block
Block
bandgap
imcmodes
Fix7
Fix8
imcbias1
imcbias2
imcbias3
Imcbias4
Fix9
Fix10
dataconfig1
dataconfig2
Fix11
dacvrefadc
Fix12
Fix13
Fix14
datachannel0_1
datachannel0_2
datachannel1_1
Register Name Address [6..0]
14
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Field
[5:3]
[7:0]
[7:0]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[7:0]
[7:0]
[1:0]
[7:6]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[5:4]
[7:0]
[0]
[1]
[2]
[0]
[1]
[2]
[3]
[4]
[5]
[2]
[3]
[4]
[5]
[0]
[1]
[2]
[3]
[0]
[1]
‘0’
‘1’
‘0’
‘000’
0
‘1’
‘1’
0
‘1’
‘0’
0x00
0x00
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
0x20
0xC0
0x00
0
0
0
0
0x03
0x2A
0
0x80
0x80
0
0
0
0
0x00
0x00
0
0
Reset Value
Power down bandgap and currents
External resistor
External voltage reference
Bandgap trimming
Power down
Enable vrefcol regulator
Enable precharge regulator
Disable internal bias for vprech
Disable column load
clkmain invert
Reserved, fixed value
Reserved, fixed value
Bias colfpn DAC buffer
Bias precharge regulator
Bias pixel precharge level
Bias column ota
Bias column unip fast
Bias column unip slow
Bias column load
Bias column precharge
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
‘1’: Enables user upload of dacvrefadc register value
‘0’: Keeps default value
Enable PRBS generation
Reserved, fixed value
Reserved, fixed value
Training pattern inserted to sync LVDS receivers
Training pattern inserted to sync LVDS receivers
Reserved, fixed value
Input to DAC to set the offset at the input of the ADC
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Bypass the data block
Enables the FPN correction
Overwrite incoming ADC data by the data in the testpat
register
Reserved, fixed value
Pattern inserted to generate a test image
Pattern inserted to generate a test image
Bypass the data block
Enables the FPN correction
Description
CYIL2SM1300AA
Page 12 of 43
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