CYIL2SC1300AA-GZDC Cypress Semiconductor Corp, CYIL2SC1300AA-GZDC Datasheet
CYIL2SC1300AA-GZDC
Specifications of CYIL2SC1300AA-GZDC
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CYIL2SC1300AA-GZDC Summary of contents
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... It packs 24 parallel 10-bit A/D converters with an aggregate conversion rate of 740 MSPS. On-chip digital column Ordering Information Marketing Part Number CYIL2SM1300AA-GZDC CYIL2SM1300AA-GWCES CYIL2SC1300AA-GZDC CYIL2SM1300-EVAL Note 1. Contact your local sales office for the windowless option. Cypress Semiconductor Corporation Document Number: 001-24599 Rev. *C ...
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Overview This data sheet describes the interface of the LUPA1300-2 image sensor. The SXGA resolution CMOS active pixel sensor features synchronous shutter and a maximal frame rate of 500 fps in full resolution. The readout speed is boosted by sub ...
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Photovoltaic Response Curve Figure 2. Photo Voltaic Response of LUPA 1300-2 Spectral Response Curve Document Number: 001-24599 Rev. *C Figure 3. Spectral Response of LUPA 1300-2 CYIL2SM1300AA Page [+] Feedback ...
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Figure 4. Spectral Response of LUPA 1300-2 Color Sensor 0.2 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 400 500 Document Number: 001-24599 Rev. *C 600 700 800 CYIL2SM1300AA RED GREEN NEAR RED GREEN NEAR BLUE BLUE 900 1000 Page ...
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Electrical Specifications Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. [2] Table 3. Absolute Ratings Symbol V Core digital supply voltage DIG V Analog supply voltage supply current IO ...
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Table 4. Power Supply Ratings Boldface limits apply for MIN MAX Symbol Power Supply V , GND Buffer Supply Operating voltage BUF BUF Dynamic Current Peak Current Standby current V , Sampling ...
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Table 5. Power Dissipation These specifications apply for V = 2.5V, Clock = 315 MHz, 500 fps DD Parameter Symbol Power down P DOWN Average Power Dissipation Power Table 6. AC Electrical Characteristics The following specifications apply for VDD ...
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The 6T Pixel To obtain the global shutter feature combined with a high sensitivity and good parasitic light sensitivity (PLS), implement the pixel architecture shown in Figure 6. This pixel architecture is designed µ µm ...
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Operation and Signaling Digital Signals Depending on the operation mode (Master or Slave), the pixel array of the image sensor requires different digital control signals. The function of each signal is listed in this table. Table 11. Overview of Digital ...
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Non Destructive Readout (NDR) Figure 8. Principle of Non Destructive Readout The sensor can also be read out in a nondestructive method. After a pixel is initially reset, it can be read multiple times, without being reset. You can record ...
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Table 13. Internal Registers (continued) Block Register Name Address [6..0] LVDS clk lvdsmain divider lvdspwd1 lvdspwd2 Fix6 AFE afebias afemode afepwd1 afepwd2 Bias block bandgap Image Core imcmodes Fix7 Fix8 imcbias1 imcbias2 imcbias3 Imcbias4 Document Number: 001-24599 Rev. *C Field ...
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Table 13. Internal Registers (continued) Block Register Name Address [6..0] Data Block Fix9 Fix10 dataconfig1 dataconfig2 Fix11 dacvrefadc Fix12 Fix13 Fix14 datachannel0_1 datachannel0_2 datachannel1_1 Data Block (continued) datachannel1_2 datachannel12_1 datachannel12_2 Document Number: 001-24599 Rev. *C Field Reset Value 21 [7:0] ...
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Table 13. Internal Registers (continued) Block Register Name Address [6..0] Sequencer seqmode1 56 seqmode2 57 seqmode3 58 Document Number: 001-24599 Rev. *C Field Reset Value [0] 0 Enables image capture [1] 1 ‘1’: Master mode, integration timing is generated on-chip ...
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Table 13. Internal Registers (continued) Block Register Name Address [6..0] seqmode4 59 window1_1 60 window1_2 61 window1_3 62 window1_4 63 window2_1 64 window2_2 65 window2_3 66 window2_4 67 window3_1 68 window3_2 69 window3_3 70 window3_4 71 window4_1 72 window4_2 73 ...
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Table 13. Internal Registers (continued) Block Register Name Address [6..0] tint_black_timer 85 rot_timer 86 fot_timer 87 fot_timer 88 prechpix_timer 89 prechpix_timer 90 prechcol_timer 91 rowselect_timer 92 sample_timer 93 sample_timer 94 vmem_timer 95 vmem_timer 96 delayed_rdt_timer 97 delayed_rdt_timer 98 Fix29 99 ...
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Datachannels. DatachannelX_1 and DatachannelX_2 (with X=0 to 12) are registers that allow you to enable or disable the FPN correction (DatachannelX_1[1]), and generate a test pattern if necessary (datachannelX_1[5:4] datachannelX_2[7:0]). Sequencer Block The sequencer block group registers allow enabling or ...
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Res_length (76 and 77). This register sets the length of the internal pixel array reset (how long are all pixel reset simultaneously). This value is expressed in 'number of lines clock cycles (depends on seqmode3[6]). Res_dsts_length. This register ...
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Image Sensor Timing and Readout The timing of the sensor consists of two parts. The first part is related to the exposure time and the control of the pixel. The second part is related to the read out of the ...
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Programming the Exposure Time In master mode, the exposure time is configured in two distinct methods (controlled by register seqmode3[6]): ■ #lines: Obvious, changing signals that control integration time. They are always changed during ROT to avoid any image artefacts. ...
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Slave Mode In slave mode, the register values of res_length and tint_timer are ignored. The integration time is controlled by the int_time pin. The relationship between the input pin and the integration time is shown in array goes out of ...
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Master Mode In this mode, a rising edge on int_time1 pin is used to trigger the start of integration and read out. The tint_timer defines the integration time independent of the assertion of the input pin int_time1. After the integration ...
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Reverse Scan Reverse scanning is supported in the X and Y direction. Line 0 (first line on the output) is the top line in normal mode and the bottom line in reverse scanning, as shown in Figure operation is analogous. ...
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Figure 19 shows the sequence of integration and read out for multiple windows. The handling of integration time is identical to the single window mode (except that in this case, the maximum integration time is equal to the sum of ...
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The reset levels are configured through external (power) pins. In master mode, the time stamps of the double and triple slope resets are configured in a method similar to configuring the exposure time. The time stamps are enabled through the ...
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Column FPN Correction The column FPN of the sensor is improved by the offset correction of the columns. At the start of every frame, before read out of the actual lines is done, a fixed voltage is applied at the ...
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Image Format and Read Out Protocol The active area read out by the sequencer in full frame mode is shown in line is read to enable column FPN calibration. A reference voltage is applied to the columns and the entire ...
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The following sections discuss the appearance of the output (data and synchronization codes) in several relevant configurations. Twelve output channels are connected to the 24 ADCs and handle the data. One additional channel contains all the synchronization codes for the ...
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Full Frame Mode In this operation mode, the entire sensor shown in sequencer, and the behavior of the data and sync channels (overview and detail of one line). Sequencer FOT ROT internal state Data channel Sync Channel Data Channel T ...
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This table provides a detailed overview of remapping one full row read out. Table 16. Remapping Scheme for One Row timeslot ch0 ch1 ch2 ...
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Single Window Mode Containing Timeslot 54 In this operation mode, only part of the sensor is read out, as shown by the shaded area in the single window mode that does not contain the timeslot 54, because the output synchronization ...
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Single Window Mode Not Containing Timeslot 54 In this operation mode, only part of the sensor is read out, as shown in any data from timeslot 54 read out to provide information on grey and black columns to ...
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Pin List Table 17. Pin Placement Layout (Top View 134 130 127 124 121 118 115 112 109 106 103 100 131 128 125 122 119 116 113 110 ...
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Table 18. Pin List nr Pin Name Type 1 clkoutp LVDS 2 clkoutn LVDS 3 chp[0] LVDS 4 chn[0] LVDS 5 gndlvds Supply 6 gndadc Supply 7 vddadc Supply 8 vddlvds Supply 9 chp[1] LVDS 10 chn[1] LVDS 11 chp[2] ...
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Table 18. Pin List (continued) nr Pin Name Type 43 vddadc Supply 44 vddlvds Supply 45 clkinp LVDS 46 clkinn LVDS 47 syncp LVDS 48 syncn LVDS 49 gnddig Supply 50 vdddig Supply 51 cap_vrefm Analog 52 cap_vrefp Analog 53 ...
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Table 18. Pin List (continued) nr Pin Name Type 84 pixdiode Analog 85 gndpix Supply 86 vsamp Supply 87 vresetab Supply 88 vprech Supply 89 vmemh Supply 90 vmeml Supply 91 vreset Supply 92 vresetds Supply 93 vresetts Supply 94 ...
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Table 18. Pin List (continued) nr Pin Name Type 127 spics CMOS 128 spiclk CMOS 129 spiin CMOS 130 spiout CMOS 131 mbsbus[0] Analog 132 mbsbus[1] Analog 133 refbg Analog 134 cmdmbs Analog 135 vdddig Supply 136 gndadc Supply 137 ...
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Package Information Figure 32. Package Outline Drawing with Glass The total distance from the bottom of the µPGA package (same as the PCB plane) to the top of the die surface is 19.016 mm. Document Number: 001-24599 Rev. *C CYIL2SM1300AA ...
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Package with Glass Cross Section Document Number: 001-24599 Rev. *C Figure 33. Pixel Active Area Dimensions Figure 34. Package Cross Section CYIL2SM1300AA Page [+] Feedback ...
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Die Specifications 1450 ± Document Number: 001-24599 Rev. *C Figure 35. Die Specifications 1700 ± CYIL2SM1300AA Page [+] Feedback ...
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Glass Lid The LUPA 1300-2 monochrome and color image sensor uses a glass lid without any coatings. characteristics of the glass lid. As seen in Figure 36, no infrared attenuating color filter glass is used. You must provide this filter ...
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