CYII5SM1300AB-QDC Cypress Semiconductor Corp, CYII5SM1300AB-QDC Datasheet - Page 16

• Manufacturer Part Number: CYII5SM1300AB-QDC
• Description: SENSOR IMAGE MONO CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII5SM1300AB-QDC

• Pixel Size: 6.7µm x 6.7µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 27
• Voltage - Supply: 3 V ~ 4.5 V
• Package / Case: 84-LCC
• Sensor Image Color Type: Monochrome
• Sensor Image Size Range: >= 480,000Pixels
• Sensor Image Size: 1280x1024Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 65C
• Package Type: CLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package: 84CLCC
• Image Size: 1280x1024 Pixels
• Color Sensing: Monochrome
• Operating Temperature: 0 to 65 °C
• Operating Supply Voltage: 3 to 3.6 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 15. Internal Registers
Document #: 38-05710 Rev. *H
Register
0 (0000)
1 (0001)
2 (0010)
3 (0011)
4 (0100)
5 (0101)
6 (0110)
8 (1000)
7 (0111)
11:0
11:0
11:0
11:0
10:0
10:0
10:0
Bit
7:0
6:0
10
11
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
SEQUENCER register
SHUTTER_TYPE
FRAME_CAL_MODE
LINE_CAL_MODE
CONT_CHARGE
GRAN_X_SEQ_LSB
GRAN_X_SEQ_MSB
GRAN_SS_SEQ_LSB
GRAN_SS_SEQ_MSB
KNEEPOINT_LSB
KNEEPOINT_MSB
KNEEPOINT_ENABLE
VDDR_RIGHT_EXT
NROF_PIXELS
NROF_LINES
INT_TIME
X_REG
YL_REG
YR_REG
IMAGE CORE register
TEST_EVEN
TEST_ODD
X_SUBSAMPLE
X_SWAP12
X_SWAP30
Y_SUBSAMPLE
Y_SWAP12
Y_SWAP30
AMPLIFIER register
GAIN<0>
GAIN<1>
GAIN<2>
GAIN<3>
UNITY
DUAL_OUT
STANDBY
Name
Default value <11:0>: ’000011000100’
1 = rolling shutter
0 = synchronous shutter
0 = fast
1 = slow
0 = fast
1 = slow
1 = ’Continuous’ precharge enabled
Granularity of the X sequencer clock
Granularity of the SS sequencer clock
Sets reset voltage for multiple slope operation
1 = Enables multiple slope operation in synchronous shutter mode
1 = Disables circuit that generates VDDR_RIGHT voltage; this allows the appli-
cation of an external voltage
Number of pixels to count (maximum 1280/2)
Default value <11:0>: ’001001111111’
Number of lines to count
Default value <11:0>: ’001111111111’
Integration time
Default value <11:0>: ’111111111111’
X start position (maximum 1280/2)
Default value <10:0>: ’00000000000’
Y-left start position
Default value <10:0>: ’00000000000’
Y-right start position
Default value <10:0>: ’00000000000’
Default value <7:0>: ’00000000’
Test even columns
Test odd columns
Enable sub-sampling in X-direction
Swap columns 1-2, 5-6, …
Swap columns 3-4, 7-8, …
Enable sub-sampling in Y-direction
Swap rows 1-2, 5-6, …
Swap rows 3-4, 7-8, …
Default value <6:0>: ’1010000’
Output amplifier gain setting
1 = Amplifier in unity gain mode
1 = Activates second output
0 = Amplifier in standby mode
Description
CYII5SM1300AB
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