CYII5FM1300AB-QDC Cypress Semiconductor Corp, CYII5FM1300AB-QDC Datasheet - Page 11
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CYII5FM1300AB-QDC
Manufacturer Part Number
CYII5FM1300AB-QDC
Description
SENSOR IMAGE 1.3MP CMOS 84-LCC
Manufacturer
Cypress Semiconductor Corp
Type
CMOS Imagingr
Datasheet
1.CYII5FM1300-EVAL.pdf
(35 pages)
Specifications of CYII5FM1300AB-QDC
Pixel Size
6.7µm x 6.7µm
Active Pixel Array
1280H x 1024V
Frames Per Second
27
Voltage - Supply
3 V ~ 4.5 V
Package / Case
84-LCC
Sensor Image Color Type
Monochrome
Sensor Image Size Range
>= 480,000Pixels
Sensor Image Size
1280x1024Pixels
Operating Supply Voltage (min)
3V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 65C
Package Type
CLCC
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
84
Package
84CLCC
Image Size
1280x1024 Pixels
Color Sensing
Monochrome
Operating Temperature
0 to 65 °C
Operating Supply Voltage
3 to 3.6 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
X-Addressing
Because of the high pixel rate, the X-shift register selects two
columns at a time for readout, so it runs at half the system clock
speed. All even columns are connected to bus A; all odd columns
to bus B. In the output amplifier, bus A and bus B are combined
into one stream of pixel data at system clock speed.
At the end of the row blanking time, the X_SYNC switch is closed
while all other switches are open and the decoder output is fed
to the register. The decoder loads a logical one in one of the
registers and a logical zero in the rest. This defines the starting
point of the window in the X direction. As soon as the X_SYNC
signal is released, the register starts shifting from the start
position.
When no sub-sampling is required, X_SUB is inactive. The
pointer in the shift-register moves one bit at a time.
When sub-sampling is enabled, X_SUB is activated. The shift
register moves two bits at a time. Taking into account that every
register selects two columns, hence two pixels sub-sampling
results in the pattern ’XXOOXXOO’ when eight pixels are
considered. Suppose the columns are numbered from left to right
starting with 0 (zero) and sub-sampling is enabled:
Figure 9. Column Structure
If columns 1 and 2, 5 and 6, 9 and 10 … are swapped using the
SWAP_12 switches, a normal sub-sampling pattern of
’XOXOXOXO’ is obtained.
If columns 3 and 4, 7 and 8, 11 and 12 … are swapped using the
SWAP_30 switches, the pattern is ’OXOXOXOX’.
If both the SWAP_12 and SWAP_30 switches are closed, pattern
’OOXXOOXX’ is obtained.
Document #: 38-05710 Rev. *H
SYS_CLOCK
X_SYNC
X_SUB
X_SWAP30
X_SWAP12
BUS_A
BUS_B
1/2
Reg(n)
A
COL(i)
B
DEC(n+1)
Reg(n+1)
COL(i+1)
A
COL(i+2)
B
DEC(n+2)
Reg(n+2)
COL(i+3)
A
B
Column
amplifiers
Output
amplifier
Figure 10. Row Structure
Because every register addresses two columns at a time, the
addressable pixels range in sub-sample mode is from zero to half
the maximum number of pixels in a row (only even values). For
instance: 0, 2, 4, 6, 8… 638.
Table 11. X–Sub-sampling Patterns
Y-addressing
For symmetry reasons, the sub-sampling modes in the
Y-direction are the same as in X-direction.
Table 12. Y–Sub-Sampling Patterns
In normal mode, the pointer for the pixel row is shifted one at a
time.
When sub-sampling is enabled, Y_SYNC is activated. The
Y-shift register shifts 2 succeeding bits and skips the 2 next bits.
This results in pattern ’XXOOXXOO’.
Activating Y_SWAP12 results in pattern ’XOXOXOXO’.
Activating Y_SWAP30 results in pattern ’OXOXOXOX’.
Activating both Y_SWAP12 and Y_SWAP30 results in pattern
’OOXXOOXX’.
The addressable pixel range when Y-sub sampling is enabled is:
0–1, 4–5, 8–9, 12–13, … 1020–1021
DEC(n+1)
DEC(n+2)
DEC(n+3)
DEC(n+4)
X_SUB
Y_SUB
0
1
1
1
1
0
1
1
1
1
Y_SYNC Y_SUB
X_SWAP12 X_SWAP30 Sub-Sample Pattern
Y_SWAP12 Y_SWAP30 Sub-Sample Pattern
0
0
1
0
1
0
0
1
0
1
Reg(n+1)
Reg(n+2)
Reg(n+3)
Reg(n+4)
Reg(n)
Y_SWAP12
0
0
0
1
1
0
0
0
1
1
CYII5SM1300AB
Y_SWAP30
XXOOXXOO
XOXOXOXO
OXOXOXOX
OOXXOOXX
XXOOXXOO
XOXOXOXO
OXOXOXOX
OOXXOOXX
SRH
SRH
SRH
SRH
XXXXXXXX
XXXXXXXX
Page 11 of 35
ROW(n+1)
ROW(n+2)
ROW(n+3)
ROW(n+4)
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