CYII4SM1300AA-QDC Cypress Semiconductor Corp, CYII4SM1300AA-QDC Datasheet - Page 15

• Manufacturer Part Number: CYII4SM1300AA-QDC
• Description: SENSOR IMAGE MONO CMOS 84-LCC
• Manufacturer: Cypress Semiconductor Corp
• Type: CMOS Imagingr

Specifications of CYII4SM1300AA-QDC

• Package / Case: 84-LCC
• Pixel Size: 7µm² x 7µm²
• Active Pixel Array: 1286H x 1030V
• Frames Per Second: 7
• Voltage - Supply: 5V
• Operating Supply Voltage: 5 V
• Image Size: 1280 H x 1024 V
• Color Sensing: Black/White
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: IBIS4-1300-M-2; IBIS4-1300-M-2

Figure 11.
for the imager. The offset voltage is adjusted to 2 V, which corre-
sponds to the low-level voltage of the ADC. Clipping is off, and
the input signal is changed between 0 and 5 V. During offset
adjustment (when calib_s is switched from 1 -> 0 or when calib_f
is on), the input signal is at 1.2 V. This level corresponds to the
imager dark reference output. The input signal is transferred to
the output by adding a 2V offset and multiplication with the
appropriate gain. The input signal of dark pixels (at 1.2 V) corre-
Setting of the VLOW_DAC and VHIGH_DAC Reference Voltages
VLOW_DAC & VHIGH_DAC are the reference voltages for the DAC. They represent the 0000 resp. 1111 code. The internal series
resistance is about 1.3 kOhms. They can be connected as in
Analog-to-Digital Converter
The IBIS4-1300 has a 10-bit Flash analog-to-digital converter running nominally at 10 Msamples/s. The ADC is electrically separated
from the image sensor. The input of the ADC ("IN_ADC") should be tied externally to the OUTPUT of the output amplifier.
Table 6. ADC Specifications
Note
Document Number: 38-05707 Rev. *C
4. Project partners have demonstrated 20 MHz data rate by careful timing and by decreasing some or all of the resistors on NBIAS* and PBIAS*.
Delay of digital circuitry (Td, 40 pF load)
Input setup time (Ts) for a stable LSB
DNL (linear conversion mode)
INL (linear conversion mode)
Power dissipation at 10 MHz
shows the output characteristic curve in a typical case
Nominal data rate
Input capacitance
Conversion law
Quantization
Input range
Figure 12. Suggested Circuit for High and Low References of DAC
< 100 ns before falling edge of clock
< 50 ns after falling edge of clock
Linear / Gamma-corrected
107 mA, 535 mW
10 Msamples/s
< 20 pF
2 to 4V
10 Bits
Figure
VHIGH_DAC
About 2.3 V
VLOW_DAC
About 1 V
sponds with 2 V at the output. Higher input signals are amplified.
The curves for 3 typical gain settings are shown (unity gain,
setting 3, 7, and11).
Again, as can be seen on the above figure, the applied input
signal during the output amplifier calibration (by 'CALIB_S' or
'CALIB_F') is the reference level to which the signal is amplified.
During this calibration, a stable input is required.
12., and decoupled to ground.
4
CYII4SM1300AA
Page 15 of 35
[+] Feedback