AD6636BBC Analog Devices Inc, AD6636BBC Datasheet - Page 46

• Manufacturer Part Number: AD6636BBC
• Description: IC RSP 6CHAN 150MSPS 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636BBC

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6636
Parallel IQ Mode
In this mode, eight bits of I data and eight bits of Q data are
output on the data bus simultaneously during one PCLK cycle.
The I byte is the most significant byte of the port, while the
Q byte is the least significant byte. The PAIQ and PBIQ output
indicator pins are set high during the PCLK cycle. Note that if
data from multiple AGCs are output consecutively, the PAIQ
and PBIQ output indicator pins remain high until data from all
channels is output.
PxCH [2:0]
Px [15:0]
PxGAIN
PxACK
PxREQ
PCLK
PxIQ
PxCH [2:0]
Px [15:0]
PxGAIN
PxACK
PxREQ
PCLK
PxIQ
Figure 42. Parallel I/Q Mode Without an AGC Gain Word
Figure 43. Parallel I/Q Mode with an AGC Gain Word
t
DPREQ
Rev. A | Page 46 of 80
t
DPREQ
LOGIC LOW 0
t
t
DPP
DPIQ
t
Q [15:8]
I [15:8]
DPCH
PxCH [2:0] = CHANNEL NO.
The PACH[2:0] and PBCH[2:0] pins provide a 3-bit binary value
indicating the source (AGC number) of the data currently being
output. Figure 42 is the timing diagram for parallel I/Q mode.
When an output data sample is available for output from an
AGC, the parallel port initiates the transfer by pulling the
PxREQ signal high. In response, the processor receiving the
data needs to pull the PxACK signal high, acknowledging that it
is ready to receive the signal.
PxCH [2:0] =
t
t
t
DPP
Q [15:8]
DPIQ
AGC NO.
DPCH
I [15:8]
GAIN [11:0]
t
DPGAIN
0000 +