AD9863BCPRL-50 Analog Devices Inc, AD9863BCPRL-50 Datasheet - Page 5

IC FRONT-END MIXED SGNL 64-LFCSP

AD9863BCPRL-50

Manufacturer Part Number
AD9863BCPRL-50
Description
IC FRONT-END MIXED SGNL 64-LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9863BCPRL-50

Rohs Status
RoHS non-compliant
Rf Type
WLL, WLAN
Features
12-bit ADC(s), 12-bit DAC(s)
Package / Case
64-VFQFN, CSP Exposed Pad
POWER SPECIFICATIONS
Analog and digital supplies = 3.3 V; F
Table 3.
Parameter
POWER SUPPLY RANGE
ANALOG SUPPLY CURRENTS
DIGITAL SUPPLY CURRENTS
DIGITAL SPECIFICATIONS
Table 4.
Parameter
LOGIC LEVELS
DIGITAL PIN
Analog Supply Voltage (AVDD)
Digital Supply Voltage (DVDD)
Driver Supply Voltage (DRVDD)
Tx Path (20 mA Full-Scale Outputs)
Tx Path (2 mA Full-Scale Outputs)
Rx Path (50 MSPS)
Rx Path (50 MSPS, Low Power Mode)
Rx Path (20 MSPS, Low Power Mode)
Tx Path, Power-Down Mode
Rx Path, Power-Down Mode
PLL
Tx Path, 1× Interpolation,
Tx Path, 2× Interpolation,
Tx Path, 4× Interpolation,
Rx Path Digital, Half-Duplex 24 Mode
Input Logic High Voltage, V
Input Logic Low Voltage, V
Output Logic High Voltage, V
Output Logic Low Voltage, V
Input Leakage Current
Input Capacitance
Minimum RESET Low Pulse Width
Digital Output Rise/Fall Time
50 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
100 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
200 MSPS DAC Update for Both DACs,
Half-Duplex 24 Mode
IL
IH
OL
OH
(1 mA Load)
(1 mA Load)
CLKIN1
= F
CLKIN2
= 50 MHz; PLL 4× setting; normal timing mode.
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Rev. A | Page 5 of 40
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
V
V
V
V
V
V
V
V
V
V
V
V
Min
DRVDD − 0.7
DRVDD − 0.6
5
2.8
3
Min
2.7
2.7
2.7
Typ
Max
0.4
0.4
12
4
Typ
70
20
103
69
55
2
5
12
20
50
80
15
Unit
V
V
V
V
µA
pF
Input clock cycles
ns
Max
3.6
3.6
3.6
AD9863
V
mA
mA
mA
mA
Unit
V
V
mA
mA
mA
mA
mA
mA
mA
mA

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