AD9861BCP-80 Analog Devices Inc, AD9861BCP-80 Datasheet - Page 33

• Manufacturer Part Number: AD9861BCP-80
• Description: IC FRONT-END MIXED SGNL 64-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9861BCP-80

• Rohs Status: RoHS non-compliant
• Rf Type: WLL, WLAN
• Features: 10-bit ADC(s), 10-bit DAC(s)
• Package / Case: 64-VFQFN, CSP Exposed Pad

mode. Both the U10 and L10 buses are used on the AD9861.
The logic level of the Tx/ Rx selector (controlled through the
IFACE1 pin) is used to configure the buses for Rx outputs
(during Rx operation) or as Tx inputs (during Tx operation). A
single pin is used to output the clocks for Rx and Tx data
latching (from the IFACE3 pin), depending on which path is
enabled. Clone mode requires interpolation of 2× or 4×.
The following notes provide a general description of the clone
mode configuration. For more information, refer to Table 16.
Note the following about the Tx path in clone mode:
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Note the following about the Rx path in clone mode:
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Table 14. Mode Pin Names and Functions
Pin Name
RxPwrDwn
TxPwrDwn
Tx/Rx (IFACE1)
ADC_LO_PWR
SPI_Bus_Enable
(SPI_CS)
FD/HD
10/20 only valid for
HD mode
Interp0 and Interp1
Interpolation rate of 2× or 4× can be programmed with
mode pins or SPI.
Max DAC update rate = 200 MSPS.
Max Tx input data rate = 80 MSPS/channel (160 MSPS
interleaved).
TxSYNC is used to direct Tx input data.
TxSYNC = high indicates channel Tx_A data.
TxSYNC = low indicates channel Tx_B data.
Buffered Tx clock output (from IFACE3 pin) uses one
rising edge per interleaved Tx sample.
ADC CLK Div register can be used to divide down the
clock driving the ADC, which accepts up to 50 MHz
(AD9861-50) or up to 80 MHz (AD9851-80).
Duration
Permanent
Permanent
Permanent only for
HD Flex I/O interface
Defined at Reset or
Power-Up
Defined at Reset or
Power-Up
Defined at Reset or
Power-Up
Defined at Reset or
Power-Up
Defined at Reset or
Power-Up
Function
When high, digital clocks to Rx block are disabled. Analog circuitry that require <10 µs to
power up are powered off.
When high, digital clocks to Tx block are disabled (PLL remains powered to maintain
output clock with an optional SPI shut off). Analog circuitry that require <10 µs to power
up are powered off.
When high, digital clocks to Tx block are disabled (PLL remains powered to maintain
output clock with an optional SPI shutoff). Tx analog blocks remain powered up unless
Tx_PwrDwn is asserted.
When low, digital clocks to Rx block are disabled. Rx analog circuitry remain powered up
unless Rx_PwrDwn is asserted.
When enabled, this bit scales the ADC power-down by 40%.
This function is controlled through the SPI_CS pin. This pin must remain low to maintain
mode pin functionality (the SPI port remains nonfunctional). This pin must be high when
coming out of reset to enable the SPI.
Configures the flex I/O for FD or HD mode. This control applies only if the SPI bus is
disabled.
If the flex I/O bus is in HD mode, this bit is used to configure parallel or interleaved data
mode. This control applies only if the SPI bus is disabled.
The Interp1 and Interp0 bits configure the PLL and the interpolation rate to 1× [00], 2×
[01], or 4× [10]. This control applies only if the SPI bus is disabled.
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Configuring with Mode Pins
The flexible interface can be configured with or without the SPI,
although more options and flexibility are available when using
the SPI to program the AD9861. Mode pins can be used to
power down sections of the device, reduce overall power consump-
tion, configure the flexible I/O interface, and program the
interpolation setting. The SPI register map, which provides
many more options, is discussed in the Configuring with SPI
section.
Mode Pins/Power-Up Configuration Options
Various options are configurable at power-up through mode
pins, and also through control pins for power-down modes. The
logic value of the configuration mode pins are latched when the
device is brought out of reset (rising edge of RESET ). The mode
pin names and their functions are shown in Table 14. Table 15
provides a detailed description of the mode pins.
Max ADC sampling rate = 50 MSPS (AD9861-50) or
80 MSPS (AD9861-80).
Output data rate = ADC sample rate, that is, two 10-bit
parallel outputs per one buffer Rx clock output cycle.
The Rx_A output data is output on L10 bus; the Rx_B
output data is output on U10 bus.
AD9861