EVAL-ADF7021-NDBEZ Analog Devices Inc, EVAL-ADF7021-NDBEZ Datasheet - Page 16

• Manufacturer Part Number: EVAL-ADF7021-NDBEZ
• Description: 426MHz To 429 MHz, External L
• Manufacturer: Analog Devices Inc
• Type: Transceiver, FSKr

Specifications of EVAL-ADF7021-NDBEZ

• Frequency: 420MHz ~ 440MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7021-N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5835434A

ADF7021-N
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12, 19, 22
13 to 18
20, 21, 23
24
25
26
27
28
Mnemonic
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFINB
R
VDD4
RSET
CREG4
GND4
MIX_I, MIX_I,
MIX_Q, MIX_Q,
FILT_I, FILT_I
FILT_Q, FILT_Q,
TEST_A
CE
SLE
SDATA
SREAD
SCLK
LNA
Description
The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.
Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and
ground for regulator stability and noise rejection.
Voltage Supply for PA Block. Place decoupling capacitors of 0.1 μF and 100 pF as close as possible to this pin.
Tie all VDD pins together.
The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The output
should be impedance matched to the desired load using suitable components (see the Transmitter section).
Ground for Output Stage of Transmitter. All GND pins should be tied together.
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer (see the LNA/PA Matching section).
Complementary LNA Input. (See the LNA/PA Matching section.)
External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.
External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with 5% tolerance.
Regulator Voltage for LNA/MIXER Block. Place a 100 nF capacitor between this pin and GND for regulator
stability and noise rejection.
Ground for LNA/MIXER Block.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.
Chip Enable. Bringing CE low puts the ADF7021-N into complete power-down. Register values are lost when
CE is low, and the part must be reprogrammed after CE is brought high.
Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of the
four latches. A latch is selected using the control bits.
Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This pin is a high
impedance CMOS input.
Serial Data Output. This pin is used to feed readback data from the ADF7021-N to the microcontroller. The
SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 32-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
RFGND
CREG1
RFOUT
CREG4
VCOIN
RFINB
GND4
VDD1
VDD4
RSET
R
RFIN
LNA
10
11
12
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 10. Pin Configuration
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ADF7021-N
(Not to Scale)
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
CLKOUT
TxRxCLK
TxRxDATA
SWD
VDD2
CREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE