EPM7256BUC169-10N Altera, EPM7256BUC169-10N Datasheet - Page 18

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EPM7256BUC169-10N

Manufacturer Part Number
EPM7256BUC169-10N
Description
MAX 7000/S/AE/B
Manufacturer
Altera
Datasheet

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MAX 7000B Programmable Logic Device Data Sheet
18
Table 4. MAX 7000B t
Table 5. MAX 7000B In-System Programming Times for Different Test Clock Frequencies
Table 1. MAX 7000B Stand-Alone Verification Times for Different Test Clock Frequencies
EMP7032B
EMP7064B
EMP7128B
EMP7256B
EMP7512B
EMP7032B
EMP7064B
EMP7128B
EMP7256B
EMP7512B
Device
Device
EMP7032B
EMP7064B
EMP7128B
EMP7256B
EMP7512B
Device
10 MHz
10 MHz
0.00
0.01
0.01
0.02
0.03
2.13
2.13
2.14
2.17
2.21
PULSE
The programming times described in
with the worst-case method using the enhanced ISP algorithm.
Tables 5
verification times for several common test clock frequencies.
& Cycle
5 MHz
5 MHz
0.01
0.01
0.02
0.03
0.06
2.13
2.14
2.16
2.21
2.30
t
PPULSE
2.12
2.12
2.12
2.12
2.12
TCK
and
2 MHz
2 MHz
(s)
0.01
0.02
0.04
0.08
0.15
Values
Programming
2.15
2.18
2.23
2.35
2.58
6
show the in-system programming and stand alone
1 MHz
1 MHz
0.02
0.04
0.07
0.15
0.30
2.19
2.24
2.34
2.58
3.03
Cycle
120,000
222,000
466,000
914,000
70,000
f
f
TCK
TCK
PTCK
500 kHz
500 kHz
0.04
0.07
0.14
0.30
0.60
2.26
2.36
2.56
3.05
3.95
Tables 4
200 kHz
200 kHz
0.09
0.18
0.35
0.76
1.50
2.47
2.72
3.23
4.45
6.69
t
VPULSE
0.002
0.002
0.002
0.002
0.002
Stand-Alone Verification
through
(s)
100 kHz
100 kHz
11.26
0.18
0.35
0.69
1.51
3.00
2.82
3.32
4.34
6.78
Altera Corporation
6
are associated
50 kHz
50 kHz
11.44
20.40
0.36
0.70
1.38
3.02
6.00
Cycle
3.52
4.52
6.56
151,000
300,000
18,000
35,000
69,000
VTCK
Units
Units
s
s
s
s
s
s
s
s
s
s

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