EPM2210GF256I5N Altera, EPM2210GF256I5N Datasheet - Page 3
EPM2210GF256I5N
Manufacturer Part Number
EPM2210GF256I5N
Description
MAX II
Manufacturer
Altera
Datasheet
1.EPM2210GM100I.pdf
(108 pages)
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Introduction
Features
Altera Corporation
December 2007
MII51001-1.7
The MAX
0.18-µm, 6-layer-metal-flash process, with densities from 240 to 2,210
logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile
storage of 8 Kbits. MAX II devices offer high I/O counts, fast
performance, and reliable fitting versus other CPLD architectures.
Featuring MultiVolt core, a user flash memory (UFM) block, and
enhanced in-system programmability (ISP), MAX II devices are designed
to reduce cost and power while providing programmable solutions for
applications such as bus bridging, I/O expansion, power-on reset (POR)
and sequencing control, and device configuration control.
The MAX II CPLD has the following features:
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Low-cost, low-power CPLD
Instant-on, non-volatile architecture
Standby current as low as 29 µA
Provides fast propagation delay and clock-to-output times
Provides four global clocks with two clocks available per logic array
block (LAB)
UFM block up to 8 Kbits for non-volatile storage
MultiVolt core enabling external supply voltages to the device of
either 3.3 V/2.5 V or 1.8 V
MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic
levels
Bus-friendly architecture including programmable slew rate, drive
strength, bus-hold, and programmable pull-up resistors
Schmitt triggers enabling noise tolerant inputs (programmable per
pin)
Fully compliant with the Peripheral Component Interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for
3.3-V operation at 66 MHz
Supports hot-socketing
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)
circuitry compliant with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
®
II family of instant-on, non-volatile CPLDs is based on a
Chapter 1. Introduction
1–1
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