EPF6016AQC208-1N Altera, EPF6016AQC208-1N Datasheet - Page 7

• Manufacturer Part Number: EPF6016AQC208-1N
• Description: FLEX 6000
• Manufacturer: Altera

Specifications of EPF6016AQC208-1N

• Family Name: FLEX 6000
• Number Of Usable Gates: 16000
• Number Of Logic Blocks/elements: 1320
• # I/os (max): 171
• Frequency (max): 200MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1320
• Device System Gates: 16000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Figure 2. Logic Array Block
Altera Corporation
LAB or IOEs
Adjacent
To/From
Local Interconnect
Row Interconnect
The interleaved LAB structure—an innovative feature of the FLEX 6000
architecture—allows each LAB to drive two local interconnects. This
feature minimizes the use of the FastTrack Interconnect, providing higher
performance. An LAB can drive 20 LEs in adjacent LABs via the local
interconnect, which maximizes fitting flexibility while minimizing die
size. See
In most designs, the registers only use global clock and clear signals.
However, in some cases, other clock or asynchronous clear signals are
needed. In addition, counters may also have synchronous clear or load
signals. In a design that uses non-global clock and clear signals, inputs
from the first LE in an LAB are re-routed to drive the control signals for
that LAB. See
The 10 LEs in the LAB are driven by two
local interconnect areas. The LAB can drive
two local interconnect areas.
Figure
The row interconnect is
bidirectionally connected
to the local interconnect.
Figure
2.
FLEX 6000 Programmable Logic Device Family Data Sheet
3.
LEs can directly drive the row
and column interconnect.
Column Interconnect
To/From
Adjacent
LAB or IOEs
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