EPF10K50VBC356-1N Altera, EPF10K50VBC356-1N Datasheet - Page 16
EPF10K50VBC356-1N
Manufacturer Part Number
EPF10K50VBC356-1N
Description
FLEX 10KA
Manufacturer
Altera
Datasheet
1.EPF10K50VBC356-1N.pdf
(128 pages)
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FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 7
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can either be bypassed for simple adders or
be used for an accumulator function. The carry chain logic generates the
carry-out signal, which is routed directly to the carry-in signal of the next-
higher-order bit. The final carry-out signal is routed to an LE, where it can
be used as a general-purpose signal.
Figure 7. Carry Chain Operation (n-bit Full Adder)
an
bn
a1
b1
a2
b2
Carry-In
shows how an n-bit full adder can be implemented in n + 1 LEs
Carry Chain
Carry Chain
Carry Chain
Carry Chain
LUT
LUT
LUT
LUT
Register
Register
Register
Register
LEn + 1
LEn
LE1
LE2
Altera Corporation
sn
Carry-Out
s1
s2
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