DSPIC33FJ32GP204-H/ML Microchip Technology, DSPIC33FJ32GP204-H/ML Datasheet - Page 273

• Manufacturer Part Number: DSPIC33FJ32GP204-H/ML
• Description: 16-bit DSC, 44LD,32KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32GP204-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 140 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Revision D (October 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
• Changed all instances of PGCx/EMUCx and
Changed all instances of V
to V
All other major changes are referenced by their
respective section in the following table.
TABLE A-3:
© 2011 Microchip Technology Inc.
“High-Performance, 16-bit Digital Signal
Controllers”
Section 8.0 “Oscillator Configuration”
Section 10.0 “I/O Ports”
Section 15.0 “Serial Peripheral Interface
(SPI)”
Section 17.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Section 22.0 “Electrical Characteristics” Updated the Min value for parameter DC12 (RAM Retention Voltage)
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
OSCO to OSC2.
PGDx/EMUDx (where x = 1, 2 or 3) to PGECx
and PGEDx.
CAP
/V
DDCORE
Section Name
MAJOR SECTION UPDATES
DDCORE
and V
DDCORE
Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams,
which references pin connections to V
Updated the Oscillator System Diagram (see Figure 8-1).
Added Note 1 to the Oscillator Tuning (OSCTUN) register (see
Register 8-4).
Removed Table 10-1 and added reference to pin diagrams for I/O pin
availability and functionality.
Added Note 2 to the SPIx Control Register 1 (see Register 15-2).
Updated the UTXINV bit settings in the UxSTA register and added Note
1 (see Register 17-2).
and added Note 4 to the DC Temperature and Voltage Specifications
(see Table 22-4).
Updated the Min value for parameter DI35 (see Table 22-20).
Updated AD08 and added reference to Note 2 for parameters AD05a,
AD06a and AD08a (see Table 22-34).
/V
CAP
Update Description
SS
.
DS70290G-page 273