DSPIC33FJ256MC510A-E/PF Microchip Technology, DSPIC33FJ256MC510A-E/PF Datasheet - Page 37
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DSPIC33FJ256MC510A-E/PF
Manufacturer Part Number
DSPIC33FJ256MC510A-E/PF
Description
16 Bit MCU/DSP 40MIPS 256KB FLASH 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ256MC510A-E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256MC510A-E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
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4.0
The dsPIC33FJXXXMCX06A/X08A/X10A architecture
features separate program and data memory spaces,
and buses. This architecture also allows the direct
access of program memory from the data space during
code execution.
FIGURE 4-1:
2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
Note:
MEMORY ORGANIZATION
of the dsPIC33FJXXXMCX06A/X08A/
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section 3.
“Data Memory” (DS70202) and Section
4. “Program Memory” (DS70203) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
dsPIC33FJ64MCXXXA
Alternate Vector Table
Interrupt Vector Table
Device Configuration
Memory areas are not shown to scale.
(22K instructions)
GOTO Instruction
Unimplemented
Reset Address
Flash Memory
User Program
(Read ‘0’s)
Reserved
Registers
DEVID (2)
Reserved
Reserved
PROGRAM MEMORY MAP FOR dsPIC33FJXXXMCX06A/X08A/X10A DEVICES
dsPIC33FJXXXMCX06A/X08A/X10A
dsPIC33FJ128MCXXXA
Alternate Vector Table
Interrupt Vector Table
Device Configuration
(44K instructions)
GOTO Instruction
Unimplemented
Reset Address
Preliminary
Flash Memory
User Program
(Read ‘0’s)
DEVID (2)
Registers
Reserved
Reserved
Reserved
4.1
The
dsPIC33FJXXXMCX06A/X08A/X10A devices is 4M
instructions. The space is addressable by a 24-bit
value derived from either the 23-bit Program Counter
(PC) during program execution, or from table operation
or data space remapping as described in Section 4.6
“Interfacing Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (0x000000 to
0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space. Memory usage for the
dsPIC33FJXXXMCX06A/X08A/X10A family of devices
is shown in Figure 4-1.
program
Program Address Space
dsPIC33FJ256MCXXXA
Alternate Vector Table
Interrupt Vector Table
Device Configuration
(88K instructions)
Unimplemented
GOTO
Reset Address
address
Flash Memory
User Program
(Read ‘0’s)
DEVID (2)
Reserved
Registers
Reserved
Reserved
Instruction
memory
DS70594B-page 37
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x00ABFE
0x00AC00
0x0157FE
0x015800
0x02ABFE
0x02AC00
0x7FFFFE
0x800000
0xF7FFFE
0xF80000
0xF80017
0xF80010
0xFEFFFE
0xFF0000
0xFFFFFE
space
of
the
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