DSPIC33FJ16MC304-H/PT Microchip Technology, DSPIC33FJ16MC304-H/PT Datasheet - Page 5

• Manufacturer Part Number: DSPIC33FJ16MC304-H/PT
• Description: 16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304-H/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12. Module: I
13. Module: I
14. Module: Product Identification
15. Module: UART (UxE Interrupt)
© 2008 Microchip Technology Inc.
During I
operating in Slave mode transmits data to the
master, the ACKSTAT bit in the I2CxSTAT register
is set or cleared depending on whether the master
sent an ACK or NACK after the byte of data. If the
ACKSTAT bit is set, it will be cleared again after
some delay.
Work around
Store the value of the ACKSTAT bit immediately
after an I
If there are two I
them is acting as the Master receiver and the other
as the Slave transmitter. Suppose that both
devices are configured for 10-bit addressing
mode, and have the same value in the A10 and A9
bits of their addresses. When the Slave select
address is sent from the Master, both the Master
and Slave acknowledges it. When the Master
sends out the read operation, both the Master and
the Slave enter into Read mode and both of them
transmit the data. The resultant data will be the
ANDing of the two transmissions.
Work around
Use different addresses including the higher two
bits (A10 and A9) for different modules.
Revision A2 devices marked as extended
temperature range (E) devices, support only
industrial temperature range (I).
Work around
Use Revision A3 or newer devices marked as
extended temperature range (E) devices.
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
Work around
Read the error flags in the UxSTA register when-
ever a byte is received to verify the error status. In
most cases, these bits will be correct, even if the
UART error interrupt fails to occur.
2
2
C interrupt occurs.
C communication, after a device
2
2
C
C
2
C devices on the bus, one of
16. Module: UART (IrDA)
17. Module: Internal Voltage Regulator
18. Module: PSV Operations
When the UART is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA encoder/decoder
(IREN = 1), the module incorrectly transmits a data
payload of 80h as 00h.
Work around
None.
When the VREGS (RCON<8>) bit is set to a logic
‘0’, higher sleep current may be observed.
Work around
Ensure VREGS (RCON<8>) bit is set to a logic ‘1’
for device Sleep mode operation.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register indirect addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following com-
mand-line switch that implements a work around
for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
mode) with pre/post-decrement
DS80338D-page 5