DSPIC33FJ16MC304-H/ML Microchip Technology, DSPIC33FJ16MC304-H/ML Datasheet - Page 4

16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE

DSPIC33FJ16MC304-H/ML

Manufacturer Part Number
DSPIC33FJ16MC304-H/ML
Description
16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304-H/ML

Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ16MC304-H/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
7. Module: QEI Interrupt Generation
EXAMPLE 2:
8. Module: UART
9. Module: UART
DS80338D-page 4
unsigned int POSCNT_b15 = 0;
unsigned int Motor_Position = 0;
int main(void)
{
}
void __attribute__((__interrupt__)) _QEIInterrupt(void)
{
}
The Quadrature Encoder Interface (QEI) module
does not generate an interrupt when MAXCNT is
set to 0xFFFF and the following events occur:
1. POSCNT underflows from 0x0000 to 0xFFFF.
2. POSCNT stops.
3. POSCNT overflows from 0xFFFF to 0x0000.
This sequence of events occurs when the motor is
running in one direction, which causes POSCNT
to underflow to 0xFFFF. Once this happens, the
motor stops and starts to run in the opposite
direction, which generates an overflow from
0xFFFF to 0x0000. The QEI module does not
generate an interrupt when this condition occurs.
When the UART is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin is present only when
the module is transmitting. The pin is idle at all
other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or in an Idle state.
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one. This issue
does not affect the other UART configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
// ... User's code
MAXCNT = 0x7FFF;
Motor_Position = POSCNT_b15 + POSCNT;
// ... User's code
IFSxbits.QEIIF = 0;
POSCNT_b15 ^= 0x8000; // Overflow or Underflow
// Instead of 0xFFFF
// Clear QEI interrupt flag
// x=2 for dsPIC30F
// x=3 for dsPIC33F
10. Module: SPI
11. Module: I
Work around
To prevent this condition from occurring, set
MAXCNT to 0x7FFF, which will cause an interrupt
to be generated by the QEI module.
In addition, a global variable could be used to keep
track of bit 15, so that when an overflow or
underflow condition is present on POSCNT, the
variable will toggle bit 15. Example 2 shows the
code required for this global variable.
When the SPI module is enabled, setting the
DISSCK bit in the SPIxCON1 register does not
allow the user application to use the SCK pin as a
general purpose I/O pin.
Work around
None.
The BCL bit in I2CSTAT can be cleared only with
16-bit operation and can be corrupted with 1-bit or
8-bit operations on I2CSTAT.
Work around
Use 16-bit operations to clear BCL.
2
C
© 2008 Microchip Technology Inc.

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