DSPIC33FJ16MC304-E/ML Microchip Technology, DSPIC33FJ16MC304-E/ML Datasheet - Page 9

• Manufacturer Part Number: DSPIC33FJ16MC304-E/ML
• Description: 16-bit DSC, 16KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304-E/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164335 - MODULE SKT FOR 10X10 PM3 44TQFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25. Module: UART
26. Module: QEI
27. Module: QEI
EXAMPLE 2:
© 2010 Microchip Technology Inc.
AD1CON1bits.ADON = 0;
__asm__ volatile ("REPEAT #50");
__asm__ volatile ("NOP");
Sleep();
The UART module will not generate consecutive
break characters. Trying to perform a back-to-back
Break character transmission will cause the UART
module to transmit the dummy character used to
generate the first Break character instead of
transmitting the second Break character. Break
characters are generated correctly if they are
followed by non-Break character transmission.
Work around
None.
Affected Silicon Revisions
When the TQCS and TQGATE bits in the
QEIxCON register are set, a QEI interrupt should
be generated after an input pulse on the QEA
input. This interrupt is not generated in the affected
silicon.
Work around
None.
Affected Silicon Revisions
When the TQCS and TQGATE bits in the
QEIxCON register are set, the POSCNT counter
should not increment but erroneously does, and if
allowed to increment to match MAXCNT, a QEI
interrupt will be generated.
Work around
To prevent the erroneous increment of POSCNT
while
Accumulation mode, initialize MAXCNT = 0.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
running
A3
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
X
X
X
A4
A4
A4
X
X
X
the
A5
A5
A5
X
X
X
QEI
A6
A6
A6
X
X
X
in
Timer
//Disable the ADC module
//Wait 50 Tcy
//Repeat NOP 51 times
// Execute PWRSAV #0 and go to Sleep
Gated
28. Module: ADC
Note:
Note:
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around 1:
In order to remain within the I
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV
instruction.
Work around 2:
If the ADC module was previously initialized and
enabled, before entering Sleep, execute the lines
of code provided in
Affected Silicon Revisions
A2
X
The ADC module must be reinitialized by
the user application before resuming ADC
operation.
Unlike
application does not need to reinitialize
the ADC module; however, it is necessary
to re-enable the ADC module by setting
the ADON bit after waking from Sleep.
A3
X
PD
) may exceed the specifications listed
A4
X
Work
Example
A5
X
around
A6
X
2.
PD
DS80463E-page 9
1,
specifications
the
user
#0