DSPIC33FJ16MC101-I/P Microchip Technology, DSPIC33FJ16MC101-I/P Datasheet - Page 92

• Manufacturer Part Number: DSPIC33FJ16MC101-I/P
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 PDIP .300in TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC101-I/P

• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Featured Product: PIC24FJ/33FJ MCUs & dsPIC® DSCs
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 15
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Details

dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
REGISTER 7-11:
DS70652C-page 92
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
INT2IE: External Interrupt 2 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
INT1IE: External Interrupt 1 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
CMPIE: Comparator Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
MI2C1IE: I2C1 Master Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U-0
U-0
—
—
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
INT2IE
R/W-0
U-0
—
INT1IE
U-0
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CNIE
U-0
U-0
—
CMPIE
R/W-0
U-0
—
© 2011 Microchip Technology Inc.
x = Bit is unknown
MI2C1IE
R/W-0
U-0
—
SI2C1IE
R/W-0
U-0
—
bit 8
bit 0