DSPIC33FJ16GS404T-I/ML Microchip Technology, DSPIC33FJ16GS404T-I/ML Datasheet - Page 13
![16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ16GS404T-I/ML
Manufacturer Part Number
DSPIC33FJ16GS404T-I/ML
Description
16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ06GS101-ISO.pdf
(346 pages)
2.DSPIC33FJ06GS101-ISO.pdf
(18 pages)
3.DSPIC33FJ06GS101-ISO.pdf
(16 pages)
Specifications of DSPIC33FJ16GS404T-I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
33. Module: Reserved
34. Module: PWM
© 2010 Microchip Technology Inc.
The issue in the previous version of the document
has been removed.
The High-Speed PWM provides a feature to
update the PWM duty cycle at any time during the
PWM period. The new duty cycle should take
effect:
• On the next PWM period when immediate duty
• On the same PWM period when immediate
However, when the immediate duty cycle updates
are disabled and the duty cycle update coincides
with a PWM period roll-over, the PWM output may
be corrupted and exhibit a 100% duty cycle for one
PWM period. The new duty cycle value will take
effect on the next PWM period.
Work around
Enable
configuring PWMCONx<IUE> = 1.
Affected Silicon Revisions
A2
cycle updates are disabled
(PWMCONx<IUE> = 0).
duty cycle updates are enabled
(PWMCONx<IUE> = 1).
X
A3
X
immediate
A4
X
duty
cycle
updates
by
35. Module: JTAG
In JTAG mode, the TMS pin will not have an active
pull-up as required by the JTAG specification.
Instead, the pull-up function will be enabled on the
TCK pin.
Work around
An external pull-up resistor can be connected to
the TMS pin to ensure that the signal does not
enter a tri-state condition when in JTAG mode.
There is no work around for the wrongly enabled
pull-up function on the TCK pin.
Affected Silicon Revisions
A2
Note:
X
A3
X
This issue is only present in the
dsPIC33FJ06GS101 device.
A4
X
DS80439H-page 13