DSPIC33FJ12MC201-E/P Microchip Technology, DSPIC33FJ12MC201-E/P Datasheet - Page 12
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DSPIC33FJ12MC201-E/P
Manufacturer Part Number
DSPIC33FJ12MC201-E/P
Description
12 KB Flash, 1 KB RAM, 40 MIPS, 13 I/O, 16-bit Motor Control DSC, NanoWatt 20 PD
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
Specifications of DSPIC33FJ12MC201-E/P
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3.6
3.6.1
The dsPIC33F/PIC24H devices have Configuration
bits stored in twelve 8-bit Configuration registers,
aligned on even configuration memory address
boundaries. These bits can be set or cleared to select
various device configurations. There are three types of
Configuration bits: system operation bits, code-protect
bits and unit ID bits. The system operation bits
determine the power-on settings for system level
TABLE 3-2:
DS70152H-page 12
RBS<1:0>
BSS<2:0>
Bit Field
Configuration Bits Programming
OVERVIEW
dsPIC33F/PIC24H CONFIGURATION BITS DESCRIPTION
Register
FBS
FBS
Boot Segment Data RAM Code Protection
11 = No RAM is reserved for Boot Segment
10 = Small-Sized Boot RAM
[128 bytes of RAM are reserved for Boot Segment]
01 = Medium-Sized Boot RAM
[256 bytes of RAM are reserved for Boot Segment]
00 = Large-Sized Boot RAM
[1024 bytes of RAM are reserved for Boot Segment]
Boot Segment Program Memory Code Protection
111 = No Boot Segment
110 = Standard security, Small-sized Boot Program Flash
[Boot Segment ends at 0x0003FF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.
Boot Segment ends at 0x0007FF in other all other devices.]
101 = Standard security, Medium-sized Boot Program Flash
[Boot Segment ends at 0x0007FF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.
Boot Segment ends at 0x001FFF in all other devices.]
100 = Standard security, Large-sized Boot Program Flash
[Boot Segment ends at 0x000FFF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202.
Boot Segment ends at 0x003FFF in all other devices.]
011 = No Boot Segment
010 = High security, Small-sized Boot Program Flash
[Boot Segment ends at 0x0003FF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.
Boot Segment ends at 0x0007FF in all other devices.]
001 = High security, Medium-sized Boot Program Flash
[Boot Segment ends at 0x0007FF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.
Boot Segment ends at 0x001FFF in all other devices.]
000 = High security, Large-sized Boot Program Flash
[Boot Segment ends at 0x000FFF in dsPIC33FJ06GS101/102/202,
dsPIC33FJ16GS402/404/502/504, dsPIC33FJ12GP201/202,
dsPIC33FJ12MC201/202 and PIC24HJ12GP201/202 devices.
Boot Segment ends at 0x003FFF in all other devices.]
components, such as oscillator and Watchdog Timer.
The code-protect bits prevent program memory from
being read and written.
The register descriptions for the FBS, FSS, FGS,
FOSCSEL,
Configuration registers are shown in
Note 1: If any of the code-protect bits in FBS,
Description
FSS or FGS is clear, the entire device
must be erased before it can be
reprogrammed.
FOSC,
FWDT,
© 2010 Microchip Technology Inc.
FPOR
Table
and
3-2.
FICD