DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 219
![16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ128MC804-H/ML
Manufacturer Part Number
DSPIC33FJ128MC804-H/ML
Description
16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
Specifications of DSPIC33FJ128MC804-H/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b, D/A 6x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REGISTER 16-9:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13-8
bit 7
bit 6-3
bit 2
bit 1
bit 0
Note 1:
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
FLTAM
R/W-0
U-0
—
PWM2 supports only one PWM I/O pin pair.
Unimplemented: Read as ‘0’
FAOVxH<3:1>:FAOVxL<3:1>: Fault Input A PWM Override Value bits
1 = The PWM output pin is driven active on an external Fault input event
0 = The PWM output pin is driven inactive on an external Fault input event
FLTAM: Fault A Mode bit
1 = The Fault A input pin functions in the Cycle-by-Cycle mode
0 = The Fault A input pin latches all control pins to the programmed states in PxFLTACON<13:8>
Unimplemented: Read as ‘0’
FAEN3: Fault Input A Enable bit
1 = PWMxH3/PWMxL3 pin pair is controlled by Fault Input A
0 = PWMxH3/PWMxL3 pin pair is not controlled by Fault Input A
FAEN2: Fault Input A Enable bit
1 = PWMxH2/PWMxL2 pin pair is controlled by Fault Input A
0 = PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A
FAEN1: Fault Input A Enable bit
1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input A
0 = PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A
U-0
U-0
—
—
PxFLTACON: FAULT A CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
FAOV3H
R/W-0
U-0
—
FAOV3L
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FAOV2H
R/W-0
U-0
—
(1)
FAOV2L
FAEN3
R/W-0
R/W-0
x = Bit is unknown
FAOV1H
FAEN2
R/W-0
R/W-0
DS70291E-page 219
FAOV1L
FAEN1
R/W-0
R/W-0
bit 8
bit 0
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