DSPIC33FJ128MC706T-I/PT Microchip Technology, DSPIC33FJ128MC706T-I/PT Datasheet - Page 201

IC,DSP,16-BIT,CMOS,TQFP,64PIN,PLASTIC

DSPIC33FJ128MC706T-I/PT

Manufacturer Part Number
DSPIC33FJ128MC706T-I/PT
Description
IC,DSP,16-BIT,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC706T-I/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ128MC706T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
REGISTER 18-3:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN
R/W-0
U-0
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
Unimplemented: This bit must not be set to ‘1’ by the user application
SPIFSD
R/W-0
U-0
SPIxCON2: SPIx CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
FRMPOL
R/W-0
U-0
dsPIC33FJXXXMCX06/X08/X10
U-0
U-0
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
U-0
U-0
U-0
U-0
x = Bit is unknown
FRMDLY
R/W-0
U-0
DS70287C-page 199
U-0
U-0
bit 8
bit 0

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