DSPIC33FJ128MC706A-H/MR Microchip Technology, DSPIC33FJ128MC706A-H/MR Datasheet - Page 201
![16 Bit MCU/DSP 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm TUBE](/photos/12/13/121325/c04-149_mr_sml.jpg)
DSPIC33FJ128MC706A-H/MR
Manufacturer Part Number
DSPIC33FJ128MC706A-H/MR
Description
16 Bit MCU/DSP 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ64MC506A-IPT.pdf
(352 pages)
Specifications of DSPIC33FJ128MC706A-H/MR
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
64-VFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 201 of 352
- Download datasheet (3Mb)
REGISTER 18-3:
2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN
R/W-0
U-0
—
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled (SSx pin used as frame Sync pulse input/output)
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame Sync pulse input (slave)
0 = Frame Sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame Sync pulse is active-high
0 = Frame Sync pulse is active-low
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame Sync pulse coincides with first bit clock
0 = Frame Sync pulse precedes first bit clock
Unimplemented: This bit must not be set to ‘1’ by the user application.
SPIFSD
R/W-0
U-0
—
SPIxCON2: SPIx CONTROL REGISTER 2
dsPIC33FJXXXMCX06A/X08A/X10A
W = Writable bit
‘1’ = Bit is set
FRMPOL
R/W-0
U-0
—
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
U-0
U-0
—
—
x = Bit is unknown
FRMDLY
R/W-0
U-0
—
DS70594B-page 201
U-0
U-0
—
—
bit 8
bit 0
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