DSPIC33FJ128MC204T-I/ML Microchip Technology, DSPIC33FJ128MC204T-I/ML Datasheet - Page 423
![16-bit DSC, 128KB Flash,Motor,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ128MC204T-I/ML
Manufacturer Part Number
DSPIC33FJ128MC204T-I/ML
Description
16-bit DSC, 128KB Flash,Motor,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128MC204T-I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ128MC204T-I/MLTR
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Revision E (January 2011)
This revision includes typographical and formatting
changes throughout the data sheet text. In addition, the
Preliminary marking in the footer was removed.
All instances of V
All other major changes are referenced by their
respective section in the following table.
TABLE A-4:
© 2011 Microchip Technology Inc.
“High-Performance, 16-Bit Digital Signal
Controllers”
Section 2.0 “Guidelines for Getting Started
with 16-bit Digital Signal Controllers”
Section 4.0 “Memory Organization”
Section 9.0 “Oscillator Configuration”
Section 22.0 “10-bit/12-bit Analog-to-Digital
Converter (ADC1)”
Section 28.0 “Special Features”
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Section Name
DDCORE
MAJOR SECTION UPDATES
have been removed.
The high temperature end range was updated to +150ºC (see
“Operating
Updated the title of
Connection (V
The frequency limitation for device PLL start-up conditions was
updated in
Start-up”.
The second paragraph in
The All Resets values for the following SFRs in the Timer Register
Map were changed (see
• TMR1
• TMR2
• TMR3
• TMR4
• TMR5
Added Note 3 to the OSCCON: Oscillator Control Register (see
Register
Added Note 2 to the CLKDIV: Clock Divisor Register (see
Register
Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see
Register
Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see
Register
Added Note 1 to the ACLKCON: Auxiliary Control Register (see
Register
Updated the V
(see
Added a new paragraph and removed the third paragraph in
Section 28.1 “Configuration
Added the column “RTSP Effects” to the dsPIC33F Configuration
Bits Descriptions (see
Figure 22-1
9-1).
9-2).
9-3).
9-4).
9-5).
Section 2.7 “Oscillator Value Conditions on Device
Range:”).
REFL
CAP
and
)”.
Section 2.3 “CPU Logic Filter Capacitor
references in the ADC1 module block diagrams
Figure
Table
Update Description
Table
Section 2.9 “Unused I/Os”
28-2).
22-2).
Bits”.
4-5):
DS70291E-page 423
was updated.
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