DSPIC33FJ128GP204-E/ML Microchip Technology, DSPIC33FJ128GP204-E/ML Datasheet - Page 143
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DSPIC33FJ128GP204-E/ML
Manufacturer Part Number
DSPIC33FJ128GP204-E/ML
Description
16-bit DSC, 128KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128GP204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP204-E/ML
Manufacturer:
Microchip Technology
Quantity:
135
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9.1.4
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in
The output of the primary oscillator or FRC, denoted as
‘F
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale
PLLPRE<4:0> bits (CLKDIV<4:0>).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M,’
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor
‘N2.’ This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(F
generates device operating speeds of 6.25-40 MIPS.
FIGURE 9-2:
© 2011 Microchip Technology Inc.
Source (Crystal, External Clock
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
IN
OSC
or Internal RC)
’, is divided down by a prescale factor (N1) of 2, 3,
Note 1: This frequency range must be satisfied at all times.
) is in the range of 12.5 MHz to 80 MHz, which
factor
PLL CONFIGURATION
‘N1’
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 PLL BLOCK DIAGRAM
Figure
is
9-2.
selected
Divide by
PLLPRE
2-33
N1
0.8-8.0 MHz
using
the
X
(1)
For a primary oscillator or FRC oscillator, output ‘F
the PLL output ‘F
EQUATION 9-2:
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL.
• If PLLPRE<4:0> = 0, then N1 = 2. This yields a
• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a
• If PLLPOST<1:0> = 0, then N2 = 2. This provides
EQUATION 9-3:
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
VCO output of 5 x 32 = 160 MHz, which is within
the 100-200 MHz ranged needed.
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
Divide by
PLLDIV
2-513
VCO
F
CY
M
100-200 MHz
=
F
-------------
OSC
2
F
F
VCO
OSC
OSC
=
’ is given by:
=
1
-- -
2
PLLPOST
F
XT WITH PLL MODE
EXAMPLE
⎛
⎝
(1)
Divide by
F
10000000 32
----------------------------------- -
OSC
2, 4, 8
IN
N2
•
2 2
CALCULATION
⎛
⎝
•
-------------------- -
N1 N2
•
M
12.5-80 MHz
•
DS70292E-page 143
⎞
⎠
⎞
⎠
=
40MIPS
(1)
F
OSC
IN
’,
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