DSPIC33EP256MU806-I/PT Microchip Technology, DSPIC33EP256MU806-I/PT Datasheet - Page 439

• Manufacturer Part Number: DSPIC33EP256MU806-I/PT
• Description: 64 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 64 TQFP 10x10x1mm TRA
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU806-I/PT

• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 51
• Flash Memory Size: 280KB
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 64
• Rohs Compliant: Yes
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 29-2:
© 2009-2011 Microchip Technology Inc.
WDTPOST<3:0>
Note 1:
FPWRT<2:0>
APLK<1:0>
ALTI2C2
BOREN
WDTPRE
Bit Field
PLLKEN
ALTI2C1
JTAGEN
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
AWRP
APL
2:
This bit is not available on dsPIC33EP256MU806 (64-pin) devices.
BOR should always be enabled for proper operation (BOREN = 1).
(2)
(1)
CONFIGURATION BITS DESCRIPTION (CONTINUED)
Register
FWDT
FWDT
FWDT
FPOR
FPOR
FPOR
FPOR
FICD
FAS
FAS
FAS
RTSP Effect
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
1 = Clock switches to the PLL source will wait until the PLL lock
0 = Clock switch will not wait for PLL lock
Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
Auxiliary Segment Key bits
These bits must be set to ‘00’ if AWRP = 1 and APL = 1.
These bits must be set to ‘11’ for any other value of the AWRP and
APL bits.
Any mismatch between either the AWRP or APL bits, and the APLK
bits (as described above), will result in a code protection getting
enabled for the Auxiliary Segment. A Flash bulk erase will be
required to unlock the device.
Auxiliary Segment Code-protect bit
1 = Auxiliary program memory is not code-protected
0 = Auxiliary program memory is code-protected
1 = Auxiliary program memory is not write-protected
0 = Auxiliary program memory is write-protected
Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
Power-on Reset Timer Value Select bits
111 = PWRT = 128 ms
110 = PWRT = 64 ms
101 = PWRT = 32 ms
100 = PWRT = 16 ms
011 = PWRT = 8 ms
010 = PWRT = 4 ms
001 = PWRT = 2 ms
000 = PWRT = Disabled
Brown-out Reset (BOR) Detection Enable bit
1 = BOR is enabled
0 = BOR is disabled
1 = I2C2 mapped to SDA2/SCL2 pins
0 = I2C2 mapped to ASDA2/ASCL2 pins
1 = I2C1 mapped to SDA1/SCL1 pins
0 = I2C1 mapped to ASDA1/ASCL1 pins
JTAG Enable bit
1 = JTAG enabled
0 = JTAG disabled
PLL Lock Wait Enable bit
Auxiliary Segment Write-protect bit
Alternate I
Alternate I
Preliminary
signal is valid
2
2
C™ pins for I2C2
C pins for I2C1
Description
DS70616D-page 439