CYWUSB6935-48LTXI Cypress Semiconductor Corp, CYWUSB6935-48LTXI Datasheet - Page 15
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CYWUSB6935-48LTXI
Manufacturer Part Number
CYWUSB6935-48LTXI
Description
CYWUSB6935-48LTXI
Manufacturer
Cypress Semiconductor Corp
Series
WirelessUSB™r
Specifications of CYWUSB6935-48LTXI
Frequency
2.4GHz
Data Rate - Maximum
62.5kbps
Modulation Or Protocol
GFSK
Applications
General Purpose
Power - Output
0dBm
Sensitivity
-95dBm
Voltage - Supply
2.7 V ~ 3.6 V
Current - Receiving
57.7mA
Current - Transmitting
69.1mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Product Depth (mm)
7mm
Product Length (mm)
7mm
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (typ)
3V
Operating Supply Voltage (max)
3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Compliant
Other names
428-2985
Table 16. Transmit SERDES Interrupt Status
Document #: 38-16008 Rev. *E
Note
7:4 Reserved These bits are reserved. This register is read-only.
Bit
4. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The status
3 Underflow The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data register
2 Overflow The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data register
1 Done
0
bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These registers
are read-only.
Empty
Name
7
Addr: 0x0E
(Reg 0x0F) has occurred.
1 = Underflow Interrupt pending
0 = No Underflow Interrupt pending
This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An underflow
occurs when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit SERDES
Data register (Reg 0x0F). This will only assert after the transmitter has transmitted at least one bit. This bit is cleared
by reading the Transmit Interrupt Status register (Reg 0x0E).
(0x0F) has occurred.
1 = Overflow Interrupt pending
0 = No Overflow Interrupt pending
This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow
occurs when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous data
has been sent. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).
The Done bit is used to signal the end of a data transmission.
1 = Done Interrupt pending
0 = No Done Interrupt pending
This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This will
only assert after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit Interrupt
Status register (Reg 0x0E)
The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied.
This IRQ will assert when the transmit serdes is empty. When this IRQ is asserted it is ok to write to the Transmit SERDES Data
register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear this IRQ. It will be set when the data is loaded
into the transmitter, and it is ok to write new data.
1 = Empty Interrupt pending
0 = No Empty Interrupt pending
6
Reserved
5
[4]
REG_TX_INT_STAT
4
Description
Underflow
3
Overflow
2
Done
1
CYWUSB6935
Default: 0x00
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