CY8CTST200A-48LTXIT Cypress Semiconductor Corp, CY8CTST200A-48LTXIT Datasheet - Page 188
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CY8CTST200A-48LTXIT
Manufacturer Part Number
CY8CTST200A-48LTXIT
Description
CY8CTST200A-48LTXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200A-48LTXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
38
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-QFN
Processor Series
CY8CTxx2xxA
Core
M8C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PRTxDR
21.3
The following registers are all in bank 0 and are listed in address order. An ‘x’ before the comma in the register’s address indi-
cates that the register can be accessed in Bank 0 and Bank 1, independent of the XIO bit in the CPU_F register. Registers
that are in both Bank 0 and Bank 1 are listed in address order in Bank 0. For example, the RDIxLT1 register has an address
of x,B4h and is listed only in Bank 0 but is accessed in both Bank 0 and Bank 1.
21.3.1
These registers allow for write or read access, or the current logical equivalent, of pin voltage.
The upper nibble of the PRT4DR register returns the last data bus value when read. You need to mask it off before using this
information. For additional information, refer to the
Bit
7:0
188
Individual Register Names and Addresses:
PRT0DR : 0,00h
PRT4DR : 0,10h
Access : POR
Bit Name
0,00h
Data[7:0]
Name
Bank 0 Registers
PRTxDR
Port Data Registers
7
PRT1DR : 0,04h
6
Description
Write value to port or read value from port. Reads return the state of the pin, not the value in the
PRTxDR register.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
5
Register Definitions on page 59
PRT2DR : 0,08h
4
Data[7:0]
RW : 00
3
in the GPIO chapter.
PRT3DR : 0,0Ch
2
1
0,00h
0
[+] Feedback
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