CY8CTMG200A-48PVXIT Cypress Semiconductor Corp, CY8CTMG200A-48PVXIT Datasheet - Page 7

• Manufacturer Part Number: CY8CTMG200A-48PVXIT
• Description: CY8CTMG200A-48PVXIT
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200A-48PVXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Processor Series: CY8CTxx2xxA
• Core: M8C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section C: TrueTouch System
7.
8.
9.
10. Sleep and Watchdog
11. TrueTouch Module
Internal Main Oscillator (IMO)
Internal Low Speed Oscillator (ILO)
External Crystal Oscillator (ECO)
7.1
7.2
7.3
8.1
8.2
9.1
9.2
9.3
10.1 Architectural Description.........................................................................................................73
10.2 Application Overview ..............................................................................................................76
10.3 Register Definitions.................................................................................................................77
10.4 Timing Diagrams.....................................................................................................................79
11.1 Architectural Description.........................................................................................................85
Architectural Description.........................................................................................................63
Application Overview ..............................................................................................................63
7.2.1
7.2.2
Register Definitions.................................................................................................................64
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Architectural Description.........................................................................................................67
Register Definitions.................................................................................................................68
8.2.1
Architectural Description.........................................................................................................69
Application Overview ..............................................................................................................70
Register Definitions.................................................................................................................71
9.3.1
9.3.2
9.3.3
9.3.4
10.1.1 Sleep Control Implementation Logic ..........................................................................74
10.1.2 Sleep Timer................................................................................................................76
10.3.1 RES_WDT Register ..................................................................................................77
10.3.2 SLP_CFG Register ...................................................................................................77
10.3.3 SLP_CFG2 Register .................................................................................................78
10.3.4 SLP_CFG3 Register .................................................................................................78
10.3.5 Related Registers ......................................................................................................78
10.4.1 Sleep Sequence ........................................................................................................79
10.4.2 Wakeup Sequence.....................................................................................................80
10.4.3 Bandgap Refresh.......................................................................................................80
10.4.4 Watchdog Timer.........................................................................................................81
11.1.1 Types of TrueTouch Approaches ...............................................................................85
10.1.1.1 Wakeup Logic..............................................................................................74
11.1.1.1 Positive Charge Integration .........................................................................85
11.1.1.2 Relaxation Oscillator....................................................................................86
11.1.1.3 Successive Approximation ..........................................................................87
11.1.1.4 Negative Charge Integration........................................................................88
Trimming the IMO ......................................................................................................63
Engaging Slow IMO ...................................................................................................63
IMO_TR Register .......................................................................................................64
IMO_TR1 Register ....................................................................................................64
CPU_SCR1 Register .................................................................................................65
OSC_CR2 Register ...................................................................................................65
Related Registers ......................................................................................................66
ILO_TR Register .......................................................................................................68
ECO_ENBUS Register .............................................................................................71
ECO_TRIM Register .................................................................................................71
ECO_CFG Register ..................................................................................................71
Related Registers ......................................................................................................72
Contents
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