CY8C3665AXI-016 Cypress Semiconductor Corp, CY8C3665AXI-016 Datasheet - Page 98

• Manufacturer Part Number: CY8C3665AXI-016
• Description: CY8C3665AXI-016
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C36xxr

Specifications of CY8C3665AXI-016

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 67MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: CY8C36
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3.7 Universal Digital Blocks (UDBs)
PSoC Creator provides a library of prebuilt and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,
AND, OR, and so on) that are mapped to the UDB array. See the component data sheets in PSoC Creator for full AC/DC specifications,
APIs, and example code.
Table 11-53. UDB AC Specifications
Document Number: 001-53413 Rev. *K
Datapath Performance
F
F
F
PLD Performance
F
Clock to Output Performance
t
t
CLK_OUT
CLK_OUT
MAX_TIMER
MAX_ADDER
MAX_CRC
MAX_PLD
Parameter
Maximum frequency of 16-bit timer in
a UDB pair
Maximum frequency of 16-bit adder
in a UDB pair
Maximum frequency of 16-bit
CRC/PRS in a UDB pair
Maximum frequency of a two-pass
PLD function in a UDB pair
Propagation delay for clock in to data
out, see
Propagation delay for clock in to data
out, see
Figure
Figure
Description
11-61.
11-61.
Figure 11-61. Clock to Output Performance
25 °C, Vddd ≥ 2.7 V
Worst-case placement, routing,
and pin selection
Conditions
PSoC
Min
–
–
–
–
–
–
®
Typ
3: CY8C36 Family
20
–
–
–
–
–
67.01
67.01
67.01
67.01
Max
25
55
Data Sheet
Page 98 of 125
Units
MHz
MHz
MHz
MHz
ns
ns
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