CY8C3245PVI-167 Cypress Semiconductor Corp, CY8C3245PVI-167 Datasheet - Page 55
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CY8C3245PVI-167
Manufacturer Part Number
CY8C3245PVI-167
Description
CY8C3245PVI-167
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C32xxr
Datasheet
1.CY8C3244PVI-155.pdf
(119 pages)
Specifications of CY8C3245PVI-167
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART, USB
Peripherals
CapSense, DMA, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Data Converters
A/D 2x12b, D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8.2.2.1 Single Sample
In Single Sample mode, the ADC performs one sample
conversion on a trigger. In this mode, the ADC stays in standby
state waiting for the SoC signal to be asserted. When SoC is
signaled the ADC performs four successive conversions. The
first three conversions prime the decimator. The ADC result is
valid and available after the fourth conversion, at which time the
EoC signal is generated. To detect the end of conversion, the
system may poll a control register for status or configure the
external EoC signal to generate an interrupt or invoke a DMA
request. When the transfer is done the ADC reenters the standby
state where it stays until another SoC event.
8.2.2.2 Continuous
Continuous sample mode is used to take multiple successive
samples of a single input signal. Multiplexing multiple inputs
should not be done with this mode. There is a latency of three
conversion times before the first conversion result is available.
This is the time required to prime the decimator. After the first
result, successive conversions are available at the selected
sample rate.
8.2.2.3 Multi Sample
Multi sample mode is similar to continuous mode except that the
ADC is reset between samples. This mode is useful when the
input is switched between multiple signals. The decimator is
re-primed between each sample so that previous samples do not
affect the current conversion. Upon completion of a sample, the
next sample is automatically initiated. The results can be
transferred using either firmware polling, interrupt, or DMA.
More information on output formats is provided in the Technical
Reference Manual.
Document Number: 001-56955 Rev. *J
8.2.3 Start of Conversion Input
The SoC signal is used to start an ADC conversion. A digital
clock or UDB output can be used to drive this input. It can be
used when the sampling period must be longer than the ADC
conversion time or when the ADC must be synchronized to other
hardware. This signal is optional and does not need to be
connected if ADC is running in a continuous mode.
8.2.4 End of Conversion Output
The EoC signal goes high at the end of each ADC conversion.
This signal may be used to trigger either an interrupt or DMA
request.
8.3 Comparators
The CY8C32 family of devices contains two comparators in a
device. Comparators have these features:
8.3.1 Input and Output Interface
The positive and negative inputs to the comparators come from
the analog global buses, the analog mux line, the analog local
bus and precision reference through multiplexers. The output
from each comparator could be routed to any of the two input
LUTs. The output of that LUT is routed to the UDB Digital System
Interface.
Input offset factory trimmed to less than 5 mV
Rail-to-rail common mode input range (V
Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low-power
Comparator outputs can be routed to lookup tables to perform
simple logic functions and then can also be routed to digital
blocks
The positive input of the comparators may be optionally passed
through a low pass filter. Two filters are provided
Comparator inputs can be connections to GPIO or DAC output
PSoC
®
3: CY8C32 Family
SSA
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